IP Library › Granted Patent US 11,501,968
Granted Patent B2
US 11,501,968 · App. 17/093,224 · Granted Nov 15, 2022

Method for providing a semiconductor device with silicon filled gaps

Inventors: Dieter Pierreux (Dilbeek, BE); Anna Trovato (Woluwe Saint Pierre, BE); Kelly Houben (Lubbeek, BE); Steven van Aerde (Tielt-Winge, BE); Bert Jongbloed (Oud-Heverlee, BE); Wilco A. Verweij (Nijkerk, NL)
Assignee: ASM IP Holding B.V.
H01L21/0262H01L21/02532H01L21/28525H01L21/31116H01L21/76879H01L23/5226H01L23/53271H01L21/02576H01L21/02579
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Quick Facts
Patent No.
US 11,501,968
App. No.
17/093,224
Granted
Nov 15, 2022
Kind
B2
Abstract

Method for filling a gap, comprising providing in a deposition chamber a semiconductor substrate having a gap, wherein a bottom of the gap includes a crystalline semiconducting material and wherein a side wall of the gap includes an amorphous material; depositing a silicon precursor in the gap.

Claims (19)

1. A method for filling a gap, comprising:

providing in a deposition chamber a semiconductor substrate having a gap, with a bottom and mutually substantially parallel side walls, wherein a depth of the gap is at least 200 nm, wherein the gap has a width of substantially 14 nm or less, wherein the bottom of the gap includes a crystalline semiconducting material and wherein each side wall of the gap includes a same amorphous material;

depositing a silicon precursor in the gap to cause an epitaxial growth of the crystalline semiconducting material on the bottom of the gap;

providing an etchant in the gap to etch an amorphous deposition of the silicon precursor on the side walls of the gap, wherein an etch rate of the etchant on the amorphous deposition of the silicon precursor on each of the side walls of the gap is at least five times higher than an etch rate of the etchant on the crystalline semiconducting material on the bottom of the gap.

2. A method according to claim 1 , wherein the steps of depositing the silicon precursor and providing the etchant are repeated alternatingly.

3. A method according to claim 1 , wherein an etch rate of the etchant on the amorphous deposition of the silicon precursor on the side walls of the gap is at least ten times higher than an etch rate of the etchant on the crystalline semiconducting material on the bottom of the gap.

4. A method according to claim 1 , wherein the crystalline semiconducting material includes silicon, silicon-germanium or germanium.

5. A method according to claim 1 , wherein the amorphous material includes silicon oxide and/or silicon nitride.

6. A method according to claim 1 , wherein the silicon precursor includes a silane, disilane, or trisilane.

7. A method according to claim 1 , wherein the etchant includes dichlorine or hydrogen chloride.

8. A method according to claim 1 , wherein providing the etchant in the gap is done by vapour etching.

9. A method according to claim 1 , comprising the step of etching a top oxide layer from the crystalline semiconducting material on the bottom of the gap before starting depositing the silicon precursor.

10. A method according to claim 1 , wherein the step of providing a silicon precursor in the gap includes depositing a dopant in the gap.

11. A method according to claim 10 , wherein the dopant includes phosphine, arsine, or boron trichloride.

12. A method according to claim 1 , wherein the depositing of the silicon precursor and the depositing of an etching are done in a temperature range of more or less 350° C.-550° C.

13. A method according to claim 1 , wherein the deposition chamber is a process chamber of a batch furnace.

14. A semiconductor device having a gap which is filled according to a method according to claim 1 .

15. The semiconductor device according to claim 14 , wherein the filled gap is a contact plug, the filled gap providing electrical contact between two layers.

16. The semiconductor device according to claim 15 , wherein the device is a memory device.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 20, 2020
From: PIERREUX, DIETER; TROVATO, ANNA; HOUBEN, KELLY; VAN AERDE, STEVEN; JONGBLOED, BERT; VERWEIJ, WILCO
To: ASM IP HOLDING B.V.
Reel/Frame 054438/0136 →
Continuity (2)
Provisional Application 62936071 · Nov 15, 2019
Related Publication 20210151315A1 · May 20, 2021
Cited By (4)
US 12,406,881 US 12,435,417 US 12,571,095 US 12,598,928