RC time based locked voltage controlled oscillator

1. A circuit, locking a voltage controlled oscillator at a high frequency, comprising:

an adjustable current converter, coupled at an input terminal to a power source, operable to output a control signal VC at an output terminal;

a first switch coupled to the adjustable current converter;

a voltage controlled oscillator (VCO), coupled to the first switch, and operable, when in an ON state, to receive the control signal VC and output a high frequency (VHF) signal;

a digital filter coupled to the VCO and operable to receive the VHF signal;

wherein based on the VHF signal, the digital filter generates a data signal having a data value; and

a digital-to-analog converter (DAC) operable to receive the data signal from the digital filter and, based on the data value, output an adjustment signal to the adjustable current converter;

wherein the adjustable current converter adjusts the control signal based on the adjustment signal received from the DAC.

2. The circuit of claim 1 , further comprising:

a second switch coupled to the output terminal of the adjustable current converter; and

a dummy load coupled to the second switch;

wherein the dummy load dissipates energy in the control signal VC when the VCO is in an OFF state.

3. The circuit of claim 2 ,

wherein, when the first switch is in an open state, the second switch is in a closed state;

wherein the VCO provides a VCO impedance to the control signal VC;

wherein the dummy load provides a dummy load impedance to the control signal VC; and

wherein the VCO impedance is substantially equal to the dummy load impedance.

4. The circuit of claim 2 ,

wherein the circuit is enabled when the first switch is closed; and

wherein the VCO outputs the VHF signal while the circuit is enabled.

5. The circuit of claim 1 ,

wherein the digital filter comprises:

a ripple counter operable to receive the VHF signal;

an RC timer; and

a logic control circuit (LCC) operable to output a switching signal VS substantially simultaneously to the first switch, to an inverter coupled to a second switch, to the ripple counter, and to the RC timer; and

wherein the switching signal VS includes, at any given time, one of an Enable signal and a Disable signal.

6. The circuit of claim 5 ,

wherein, while the Enable signal is included in the switching signal VS,

the first switch is closed;

the VCO receives the control signal VC from the adjustable current converter; and

the VCO outputs the VHF signal having a given period.

7. The circuit of claim 5 ,

wherein, while the Enable signal is included in the switching signal VS, the ripple counter:

divides the VHF signal to generate a low frequency signal;

counts a number of pulses in the low frequency signal until an overflow condition is satisfied; and

when the overflow condition is satisfied, outputs an overflow signal OF to the LCC.

8. The circuit of claim 7 ,

wherein, while the Enable signal is included in the switching signal VS, the RC timer:

increases a voltage in an RC circuit until a threshold voltage is reached; and

upon the threshold voltage being reached, outputs a time signal.

9. The circuit of claim 8 ,

wherein, while the Enable signal is included in the switching signal VS, the LCC:

detects receipt of a first to arrive of the overflow signal OF and the time signal;

when the overflow signal OF arrives first, decreases the data value; and

when the time signal arrives first, increases the data value.

10. The circuit of claim 9 ,

wherein an increase in the data value results in an increase of the adjustment signal, which further results in an increase of the control signal VC, and which further results in an increase in a center frequency of the VHF signal output by the VCO.

11. The circuit of claim 10 ,

wherein the LCC is operable to adjust the data value based upon a window function used in determining the first to arrive of the overflow signal OF and the time signal.

12. A digital filter, locking a voltage controlled oscillator at a high frequency signal, comprising:

a ripple counter operable to receive a high frequency signal from a voltage controlled oscillator (VCO) and output an overflow signal;

an RC timer operable to output a time signal; and

a logic control circuit coupled to the ripple counter and the RC timer, comprising:

at least one data storage component;

a detector operable to detect a first receipt of the overflow signal from the ripple counter and the time signal from the RC timer; and

a digital logic element;

wherein when the time signal arrives first, the detector instructs the digital logic element to increase a data value; and

wherein, when the overflow signal arrives first, the detector instructs the digital logic element to decrease the data value; and

wherein, based on the data value, the VCO adjusts a center frequency of the high frequency signal.

13. The digital filter of claim 12 ,

wherein the ripple counter further comprises:

“N” divider stages operable to divide the high frequency signal into a low frequency signal; and

wherein the ripple counter outputs the overflow signal when a number of pulses in the high frequency signal exceeds a pulse threshold within a given period of the low frequency signal.

14. The digital filter of claim 12 ,

wherein the RC timer further comprises:

a resistor;

a capacitor; and

a comparator;

wherein, while the RC timer is enabled, the resistor and the capacitor generate a timer voltage (V RC ) that increases from a base voltage (V B ) over time to at least a threshold voltage (V TH ); and

wherein the comparator generates the time signal when the timer voltage (V RC ) equals the threshold voltage (V TH ).

15. The digital filter of claim 14 ,

wherein the threshold voltage (V TH ) is adjusted by an RC trim signal.

16. The digital filter of claim 12 ,

wherein the at least one data storage component comprises at least one flip-flop.

17. The digital filter of claim 16 ,

wherein the logic control circuit comprises at least digital logic component operable to output a switching signal VS to the ripple counter, the RC timer, and the VCO;

wherein when the switching signal VS includes an enable signal,

the logic control circuit instructs a first switch to couple the VCO with an adjustable current converter which outputs a control signal in view of an analog adjustment signal received from a digital-to-analog converter; and

wherein the logic control circuit outputs the data value in a data signal to the digital-to-analog converter;

wherein the digital-to-analog converter converts the data value from a digital formation into the analog adjustment signal.

18. A process for locking a voltage controlled oscillator at a high frequency signal comprising:

coupling an adjustable current converter to a power source;

outputting, by the adjustable current converter, a control signal VC;

closing a first switch to couple the adjustable current converter with a voltage controlled oscillator (VCO) and provide the control signal VC to the VCO;

generating, by the VCO and based on the control signal VC a high frequency (VHF) signal;

receiving the VHF signal by a digital filter;

generating, by the digital filter and based on VHF signal , a data signal having a data value;

outputting the data signal to a digital-to-analog converter (DAC);

converting, by the DAC, the data value in the data signal into an analog adjustment signal;

receiving, by the adjustable current converter, the analog adjustment signal from the DAC; and

adjusting, by the adjustable current converter and based on the received analog adjustment signal, the control signal VC; and

wherein upon adjustment of the control signal VC, a center frequency of the VHF signal generated by the VCO is modified.

19. The process of claim 18 ,

wherein the generating of the data signal by the digital filter further comprises:

counting a number of pulses of the high frequency signal occurring within a given period for a low frequency signal until a pulse threshold is reached;

wherein the low frequency signal is a result of a multi-staged division of the high frequency signal;

when the pulse threshold is reached, outputting an overflow signal to a digital logic component;

activating an analog timer circuit which increases a timer current from a base current;

when the timer current equals a threshold current, outputting to the digital logic component a time signal;

detecting, for a given period of the low frequency signal and by the digital logic component, a first to be received of the overflow signal and the time signal;

increasing the digital count when the time signal is received before the overflow signal; and

decreasing the digital count when the overflow signal is received before the time signal.

20. The process of claim 19 , further comprising:

opening the first switch; and

closing a second switch coupling the adjustable current converter with a dummy load;

wherein the second switch has an opposite state of the first switch;

wherein the second switch provides a voltage potential substantially equivalent to an input voltage potential of the VCO; and

wherein closing of the second switch during non-enabled periods of the VCO facilitate a providing of a given control signal to the VCO upon enabling of the VCO for a later arising period.