IP Library › Granted Patent US 12,192,024
Granted Patent B2
US 12,192,024 · App. 17/103,711 · Granted Jan 7, 2025

Shared memory

Inventors: Bassam N. Coury (Portland, OR); Sujoy Sen (Beaverton, OR); Thomas E. Willis (Redwood City, CA); Durgesh Srivastava (Cupertino, CA)
Assignee: Intel Corporation
H04L12/1868G06F12/0238G06F12/0813G06F12/0837G06F12/0862G06F12/0877G06F12/0891G06F12/1081G06F13/1689G06F13/28G06F13/4059H04L12/5601H04L45/74H04L49/201H04L67/1095G06F2213/28H04L2012/562
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,192,024
App. No.
17/103,711
Granted
Jan 7, 2025
Kind
B2
Abstract

Examples described herein includes a network interface controller comprising a memory interface and a network interface, the network interface controller configurable to provide access to local memory and remote memory to a requester, wherein the network interface controller is configured with an amount of memory of different memory access speeds for allocation to one or more requesters. In some examples, the network interface controller is to grant or deny a memory allocation request from a requester based on a configuration of an amount of memory for different memory access speeds for allocation to the requester. In some examples, the network interface controller is to grant or deny a memory access request from a requester based on a configuration of memory allocated to the requester. In some examples, the network interface controller is to regulate quality of service of memory access requests from requesters.

Claims (57)

1. An apparatus comprising:

a network interface controller comprising a direct memory access (DMA) circuitry, a memory interface, and a network interface, the network interface controller configurable to provide access to a first memory and a second memory, wherein:

the network interface controller is configured with amounts of memory in the first memory and the second memory associated with different memory access speeds for allocation to one or more requesters based on class of service of the one or more requesters,

a first amount of memory in the first memory is associated with a first class of service and first memory access speed,

a second amount of memory in the second memory is associated with a second class of service and second memory access speed,

the first class of service is higher than the second class of service,

the first memory access speed is higher than the second memory access speed,

the network interface controller is to access the first memory using the memory interface, and

the network interface controller is to access the second memory by transmission or receipt of Ethernet packets.

2. The apparatus of claim 1 , wherein the network interface controller is to grant or deny a memory allocation request from a requester based on a configuration of an amount of memory for one or more of the different memory access speeds for allocation to the requester.

3. The apparatus of claim 1 , wherein the network interface controller is to grant or deny a memory access request from a requester based on a configuration of memory allocated to the requester.

4. The apparatus of claim 1 , wherein the network interface controller is to regulate quality of service (QOS) of memory access requests from the one or more requesters.

5. The apparatus of claim 1 , wherein the first memory comprises a lower latency memory technology than that of the second memory.

6. The apparatus of claim 1 , wherein the first memory comprises a memory connected to the network interface controller using the memory interface.

7. The apparatus of claim 1 , wherein the second memory comprises a memory device connected to the network interface controller using a fabric or network.

8. The apparatus of claim 1 , wherein the network interface controller is permitted to configure memory allocation to the one or more requesters within a trust group and deny memory allocation to a requester outside of the trust group.

9. The apparatus of claim 1 , comprising one or more of a server, rack, or data center and wherein the one or more of a server, rack, or data center is coupled to the network interface controller and the one or more of a server, rack, or data center is to execute a requester of the one or more requesters to request allocation of an amount of memory in the first memory and/or the second memory.

10. The apparatus of claim 1 , wherein:

a first memory address range is associated a first latency level,

a second memory address range is associated a second latency level,

the second latency level is higher than the first latency level, and

the first memory address range is different than the second memory address range.

11. At least one non-transitory computer-readable medium comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to:

enable or disable a network interface device to:

manage access to a first memory and a second memory granted to a requester, wherein

the network interface device is configured with amounts of memory in the first memory and the second memory associated with different memory access speeds for allocation to one or more requesters based on class of service of the one or more requesters,

the network interface device comprises a direct memory access (DMA) circuitry, a memory interface, and network interface,

a first amount of memory in the first memory is associated with a first class of service and first memory access speed,

a second amount of memory in the second memory is associated with a second class of service and second memory access speed,

the first class of service is higher than the second class of service,

the first memory access speed is higher than the second memory access speed,

the network interface device is to access the first memory using the memory interface, and

the network interface device is to access the second memory by transmission or receipt of Ethernet packets.

12. The computer-readable medium of claim 11 , comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to:

grant or deny a memory allocation request from a requester based on a configuration of an amount of memory for different memory access speeds for allocation to the requester.

13. The computer-readable medium of claim 11 , comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to:

enable or disable the network interface device to regulate quality of service (QOS) of memory access requests from the one or more requesters.

14. The computer-readable medium of claim 11 , wherein:

the first memory comprises a local memory connected to the network interface device using a memory interface and

the second memory comprises a memory connected to the network interface device using a fabric or network.

15. A method comprising:

a network interface device providing access to a first memory and a second memory to one or more requesters, based on configured amounts of memory of different memory access speeds allocated to one or more requesters based on class of service of the one or more requesters, wherein:

the network interface device comprises a direct memory access (DMA) circuitry, a memory interface, and network interface,

a first amount of memory in the first memory is associated with a first class of service and first memory access speed,

a second amount of memory in the second memory is associated with a second class of service and second memory access speed,

the first class of service is higher than the second class of service,

the first memory access speed is higher than the second memory access speed,

the network interface device accesses the first memory using the memory interface, and

the network interface device accesses the second memory by transmission or receipt of Ethernet packets.

16. The method of claim 15 , comprising:

granting or denying, by the network interface device, a memory allocation request from a requester of the one or more requesters based on a configuration of an amount of memory for one or more of the different memory access speeds for allocation to the requester.

17. The method of claim 15 , comprising:

granting or denying, by the network interface device, a memory access request from a requester of the one or more requesters based on a configuration of memory allocated to the requester.

18. The method of claim 15 , comprising:

regulating quality of service of memory access requests from the one or more requesters.

19. The method of claim 15 , wherein the first memory comprises a lower latency memory technology than that of the second memory.

20. The method of claim 15 , wherein the second memory comprises a memory connected to the network interface device using a fabric or network.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 1, 2020
From: COURY, BASSAM N.; SEN, SUJOY; WILLIS, THOMAS E.; SRIVASTAVA, DURGESH
To: INTEL CORPORATION
Reel/Frame 054503/0538 →
Continuity (2)
Provisional Application 63115511 · Nov 18, 2020
Related Publication 20210081312A1 · Mar 18, 2021
References Cited (81)
US 6331983B1 · Haggerty et al. · 2001 [cited by applicant]
US 6502140B1 · Boivie · 2002 [cited by applicant]
US 6625121B1 · Lau et al. · 2003 [cited by applicant]
US 6625773B1 · Boivie et al. · 2003 [cited by applicant]
US 7075904B1 · Manish et al. · 2006 [cited by applicant]
US 7969980B1 · Florit et al. · 2011 [cited by applicant]
US 7987229B1 · Kinne et al. · 2011 [cited by applicant]
US 9588928B1 · Swartzentruber · 2017 [cited by applicant]
US 9959227B1 · Diamant et al. · 2018 [cited by applicant]
US 11231987B1 · Bose et al. · 2022 [cited by applicant]
US 20010021949A1 · Blightman et al. · 2001 [cited by applicant]
US 20020041594A1 · Suzuki et al. · 2002 [cited by applicant]
US 20050081080A1 · Bender et al. · 2005 [cited by applicant]
US 20050216642A1 · Lee · 2005 [cited by applicant]
US 20050238035A1 · Riley · 2005 [cited by applicant]
US 20060075057A1 · Gildea et al. · 2006 [cited by applicant]
US 20090006666A1 · Chen et al. · 2009 [cited by applicant]
US 20110035459A1 · Desai et al. · 2011 [cited by applicant]
US 20110072234A1 · Chinya et al. · 2011 [cited by applicant]
US 20110173396A1 · Sugumar et al. · 2011 [cited by applicant]
US 20130232284A1 · Akiyama et al. · 2013 [cited by applicant]
US 20140092678A1 · Feekes · 2014 [cited by examiner]
US 20150006663A1 · Huang et al. · 2015 [cited by applicant]
US 20150092539A1 · Sivabalan et al. · 2015 [cited by applicant]
US 20150134891A1 · Jo · 2015 [cited by applicant]
US 20150293881A1 · Raikin et al. · 2015 [cited by applicant]
US 20160077966A1 · Stabrawa et al. · 2016 [cited by applicant]
US 20160267053A1 · Sharp et al. · 2016 [cited by applicant]
US 20170041157A1 · Zheng · 2017 [cited by applicant]
US 20180176324A1 · Kumar et al. · 2018 [cited by applicant]
US 20180181330A1 · Kusters et al. · 2018 [cited by applicant]
US 20180239726A1 · Wang et al. · 2018 [cited by applicant]
US 20180329841A1 · Maeda · 2018 [cited by applicant]
US 20190114102A1 · Chen · 2019 [cited by examiner]
US 20190123922A1 · Suthar et al. · 2019 [cited by applicant]
US 20190278676A1 · Zou et al. · 2019 [cited by applicant]
US 20190313275A1 · Chen · 2019 [cited by examiner]
US 20190334836A1 · Ajima et al. · 2019 [cited by applicant]
US 20190394127A1 · Gerhart et al. · 2019 [cited by applicant]
US 20200004685A1 · Bernat et al. · 2020 [cited by applicant]
US 20200021492A1 · Ganguli et al. · 2020 [cited by applicant]
US 20200042358A1 · Sun et al. · 2020 [cited by applicant]
US 20200104275A1 · Sen et al. · 2020 [cited by applicant]
US 20200133909A1 · Hefty et al. · 2020 [cited by applicant]
US 20200136996A1 · Li et al. · 2020 [cited by applicant]
US 20200210360A1 · Reghunath et al. · 2020 [cited by applicant]
US 20200296057A1 · Mula et al. · 2020 [cited by applicant]
US 20200326889A1 · Norman et al. · 2020 [cited by applicant]
US 20200349074A1 · Kucherov et al. · 2020 [cited by applicant]
US 20210073151A1 · Sen et al. · 2021 [cited by applicant]
US 20210075633A1 · Sen et al. · 2021 [cited by applicant]
US 20210374073A1 · Gugnani et al. · 2021 [cited by applicant]
US 20220035736A1 · Chiang · 2022 [cited by examiner]
CN 110401599A · 2019 [cited by applicant]
WO 2015021822A1 · 2015 [cited by applicant]
International Search Report and Written Opinion for PCT Patent Application No. PCT/US21/51357, Mailed Jan. 6, 2022, 11 pages. [cited by applicant]
Extended European Search Report for Patent Application No. 21196829.2, Mailed Mar. 3, 2022, 7 pages. [cited by applicant]
“9.2.Performing Direct Memory Access (DMA) transactions”, JUNGO Connectivity, WinDriver™ PCI/ISA User's Manual, Version 14.4.0, Chapter 9. Advanced Issues, https://www.jungo.com/st/support/documentation/windriver/14.4.0… [cited by applicant]
“Chapter 9 Direct Memory Access (DMA)”, Oracle, https://docs.oracle.com/cd/E19120-01/open.solaris/819-3196/6n5ed4h06/index.html, @2010 Oracle Corporation, 25 pages. [cited by applicant]
“Direct Memory Access”, ScienceDirect, https://www.sciencedirect.com/topics/computer-science/direct-memory-access, downloaded from the internet Oct. 11, 2022, 17 pages. [cited by applicant]
“RDMA Aware Networks Programming User Manual Rev 1.7”, Mellanox Technoloiges, www.mellanox.com, Jun. 15, 2015, 216 pages. [cited by applicant]
“Rdma_cm(7)—Linux man page”, die.net, https://linux.die.net/man/7/rdma_cm, downloaded from the internet Oct. 11, 2022, 6 pages. [cited by applicant]
“The GigaIO FabreX Memory Fabric Memory Pooling Overview”, GIGAIO Technical Paper, Feb. 2020 | Rev 1.0, 8 pages. [cited by applicant]
Baker, Art, et al., “Writing a Packet-Based Slave DMA Driver”, Oreilly, Windows 200 Device Driver Book: A Guide for Programmers, Second Edition, https://www.oreilly.com/library/view/windows-2000-device/0130204315/013020… [cited by applicant]
Deierling, Kevin, “What Is a DPU ?. . . and what's the difference between a DPU, a CPU and a GPU?”, NVIDIA, https://blogs.nvidia.com/blog/2020/05/20/whats-a-dpu-data-processing-unit/, May 20, 2020, 5 pages. [cited by applicant]
Dittia, Zubin D., et al., “DMA Mechanisms for High Performance Network Interfaces”, Washington University in St. Louis, Nov. 4, 2007, 15 pages. [cited by applicant]
Goodwins, Rupert, “How direct memory access speeds Ethernet”, ZDNET, https://www.zdnet.com/article/how-direct-memory-access-speeds-ethernet/, May 1, 2003, 3 pages. [cited by applicant]
Jiang, Dave, “Introducing The Intel® Data Streaming Accelerator (Intel® DSA)”, Intel Open Source.org, https://01.org/blogs/2019/introducing-intel-data-streaming-accelerator , Nov. 20, 2019, 6 pages. [cited by applicant]
Kauffmann, Antoine, et al., “FlexNIC: Rethinking Network DMA”, University of Washington, Apr. 20, 2015, 7 pages. [cited by applicant]
European First Office Action, (EP Exam Report Article 94(3) EPC), for Patent Application No. 21198323.4, Mailed Aug. 2, 2023, 5 pages. [cited by applicant]
International Search Report and Written Opinion for PCT Patent Application No. PCT/US21/51797, Mailed Jan. 3, 2022, 11 pages. [cited by applicant]
European First Office Action, (EP Exam Report Article 94(3) EPC), for Patent Application No. 21196829.2, Mailed Oct. 24, 2023, 4 pages. [cited by applicant]
Extended European Search Report for Patent Application No. 21198323.4, Mailed Mar. 21, 2022, 7 pages. [cited by applicant]
First Office Action for U.S. Appl. No. 17/103,602, Mailed Jan. 3, 2024, 18 pages. [cited by applicant]
First Office Action for U.S. Appl. No. 17/103,674, Mailed Jan. 3, 2024, 16 pages. [cited by applicant]
MPI, “4.1 Introduction and Overview”, https://www.mpi-forum.org/docs/mpi-1.1/mpi-11-html/node64.html, MPI-1.1, Jun. 1995, 4 pages. [cited by applicant]
First Office Action for U.S. Appl. No. 17/103,781, Mailed Dec. 18, 2023, 19 pages. [cited by applicant]
Final Office Action for U.S. Appl. No. 17/103,674, Mailed Aug. 14, 2024, 19 pages. [cited by applicant]
First Office Action for U.S. Appl. No. 17/103,802, Mailed Feb. 15, 2024, 11 pages. [cited by applicant]
European Second Office Action, (EP Exam Report Article 94(3) EPC), for Patent Application No. 21198323.4, Mailed Sep. 16, 2024, 5 pages. [cited by applicant]
Extended European Search Report for Patent Application No. 21895303.2, Mailed Sep. 10, 2024, 8 pages. [cited by applicant]
Cited By (1)
US 12,613,813