Method to allow PCI host bridge (PHB) to handle pre-fetch read transactions on the PCI bus which access system memory through translation control entry (TCE) table
View Patent ↗A method, system, and computer instructions for providing valid translation entries in the TCE table for all supported DMA addresses to prevent the occurrence of system errors due to prefetching. The mechanism of the present invention reserves a page in system memory. This reserved page is made unavailable to the operating system and may not be utilized by any software in the system. The reserved page is also written with all bytes set to 0xFF. The system firmware then selects a region in system memory for the TCE table. The TCE table is initialized, with all entries within the TCE table initialized to be valid as well as contain the corresponding address of the reserved page. In this manner, all supported DMA page addresses will have valid TCE entries which translate the DMA addresses into the reserved page memory. Thus, prefetched DMA addresses will not encounter invalid DMA address translation, and crash the system.
1. A method in a data processing system for providing valid translation entries in a translation control entry table for all supported direct memory addresses, comprising:
reserving a page in system memory to form a reserved page;
writing the reserved page;
selecting a region in the system memory for the translation control entry table;
initializing all entries in the translation control entry table, wherein all entries are initialized to be valid and contain an address of the reserved panel; and
updating an entry in the translation control entry table, wherein a physical memory page replaces the reserved page when the entry is used by an operating system's device driver.
2. The method of claim 1 , further comprising:
restoring the entry in the translation control entry table with the reserved page when the entry is no longer used by an operating system.
3. The method of claim 1 , further comprising:
determining whether a direct memory address translation corresponding to the entry has been cached in a translation lookaside buffer; and
responsive to a determination that the direct memory address translation exists, clearing the direct memory address translation from the translation lookaside buffer.
4. The method of claim 1 , wherein the page in the system memory is inaccessible to an operating system running on the data processing system.
5. The method of claim 1 , wherein writing the reserved page includes setting all bytes within the reserved page to 0xFF.
6. The method of claim 1 , wherein initializing all entries to be valid includes setting all valid bits to “1”.
7. The method of claim 1 , wherein the translation control entry table comprises a 2 MB Translation Control Entry table having 512K 4-byte entries.
8. The method of claim 1 , wherein the reserved page is utilized for DMA address translation.