Transistor level input and output harmonic terminations

1. A transistor device, comprising:

a semiconductor substrate;

a transistor cell on the semiconductor substrate, the transistor cell comprising a drain finger;

a drain runner having a longitudinal axis that extends in parallel to a longitudinal axis of the drain finger, the drain runner electrically connected to the drain finger; and

a harmonic termination circuit electrically connected to the drain runner between the drain finger and an output terminal of the transistor device, the harmonic termination circuit configured to terminate signals at a harmonic frequency of a fundamental operating frequency of the transistor device,

wherein the harmonic termination circuit and the drain runner extend on the semiconductor substrate.

2. The transistor device of claim 1 , wherein the harmonic termination circuit is configured to provide a low impedance path to ground for the signals at the harmonic frequency of the fundamental operating frequency of the transistor device.

3. The transistor device of claim 1 , wherein the harmonic termination circuit comprises a wiring layer that is in between the top surface of the semiconductor substrate and the drain runner.

4. The transistor device of claim 3 , wherein the wiring layer comprises a spiral inductor.

5. The transistor device of claim 3 , wherein the wiring layer comprises a meandered trace segment.

6. The transistor device of claim 3 , wherein the wiring layer is separated from, and capacitively coupled to, a ground conductor of the transistor device.

7. The transistor device of claim 6 , wherein the ground conductor comprises a first ground conductor layer and a second ground conductor layer, and

wherein the wiring layer is at a level that is between the first ground conductor layer and the second ground conductor layer.

8. The transistor device of claim 3 , wherein the wiring layer is a first wiring layer and the transistor device further comprises a second wiring layer,

wherein the first wiring layer comprises an inductive circuit at a level that is between the drain runner and the top surface of the semiconductor substrate, and

wherein the second wiring layer is electrically coupled to the first wiring layer and is separated from and capacitively coupled to a ground conductor of the transistor device.

9. The transistor device of claim 1 , wherein the harmonic termination circuit extends on the drain runner.

10. A transistor device, comprising:

a semiconductor substrate;

a plurality of source regions and a plurality of drain regions alternately arranged on the semiconductor substrate;

a drain manifold on the semiconductor substrate; and

a harmonic termination circuit on the semiconductor substrate, wherein the harmonic termination circuit is electrically connected between a drain finger and the drain manifold output of the transistor device.

11. The transistor device of claim 10 , wherein the harmonic termination circuit comprises a wiring layer, and

wherein the wiring layer is capacitively coupled to a ground conductor of the transistor device.

12. The transistor device of claim 11 , wherein the wiring layer is physically separated from the ground conductor by a dielectric layer.

13. The transistor device of claim 10 , wherein the harmonic termination circuit comprises a wiring layer that is at a first level above the semiconductor substrate,

wherein the transistor device further comprises a drain runner extending at a second level above the semiconductor substrate and electrically connected to the drain finger,

wherein the first level is closer to a top surface of the semiconductor substrate than the second level, and

wherein the harmonic termination circuit is electrically connected to the drain runner between the drain finger and the output of the transistor device.

14. The transistor device of claim 13 , wherein the wiring layer is a first wiring layer, and further comprising a second wiring layer,

wherein the first wiring layer comprises an inductive circuit, and

wherein the second wiring layer is electrically coupled to the first wiring layer and is separated from and capacitively coupled to a ground conductor of the transistor device.

15. A transistor device, comprising:

a substrate;

a semiconductor structure on the substrate, the semiconductor structure comprising an active region that includes at least one transistor cell; and

a harmonic termination circuit electrically connected to the at least one transistor cell, the harmonic termination circuit configured to terminate signals at a harmonic frequency of a fundamental operating frequency of the transistor device,

wherein the harmonic termination circuit is positioned between a connective runner and an upper surface of the semiconductor structure.

16. The transistor device of claim 15 , wherein the harmonic termination circuit is electrically connected to the connective runner, and wherein the connective runner extends over the active region.

17. The transistor device of claim 15 , wherein the at least one transistor cell comprises a gate electrode and a drain electrode.

wherein the transistor device further comprises:

an RF input manifold connected to the gate electrode; and

an RF output manifold connected to the drain electrode, and

wherein the harmonic termination circuit is electrically connected between the at least one transistor cell and the RF output manifold or between the at least one transistor cell and the RF input manifold.

18. The transistor device of claim 15 , wherein the harmonic termination circuit comprises a wiring layer that is separated from, and capacitively coupled to, a ground conductor of the transistor device.

19. The transistor device of claim 1 , wherein the drain runner is physically separated from the drain finger.

20. The transistor device of claim 1 , wherein the harmonic termination circuit is on the semiconductor substrate at a level below the drain runner such that the harmonic termination circuit extends on the semiconductor substrate between the drain runner and the top surface of the semiconductor substrate.