Semiconductor integrated circuit device
Provided is a semiconductor integrated circuit device including a nanowire field effect transistor (FET) and having a layout configuration effective for making manufacturing the device easy. A standard cell having no logical function is disposed adjacent to a standard cell having a logical function. The standard cell includes nanowire FETs having nanowires and pads. The standard cell further includes dummy pads, which have no contribution to a logical function of a circuit.
1. A semiconductor integrated circuit device, comprising:
a first standard cell including a nanowire field effect transistor (FET) and having a logical function; and
a second standard cell disposed adjacent to the first standard cell in a first direction and having no logical function,
wherein
the nanowire FET includes:
a plurality of nanowires extending in the first direction,
a first and second pads that are respectively arranged at both ends of the plurality of nanowires in the first direction, each connected to the plurality of nanowires, and
the second standard cell includes a dummy pad having no contribution to a logical function of a circuit, and
the first pad, the second pad and the dummy pad are arranged at an equal pitch in the first direction.
2. The semiconductor integrated circuit device of claim 1 , wherein
the first pad, the second pad and the dummy pad have an equal pad width as a dimension in the first direction, have an equal pad height as a dimension in a second direction perpendicular to the first direction, and/or have a same position in the second direction.
3. The semiconductor integrated circuit device of claim 1 ,
the second standard cell further comprising a second dummy pad, and
the first pad, the second pad, the dummy pad and the second dummy pad are arranged at an equal pitch in the first direction.
4. The semiconductor integrated circuit device of claim 3 ,
the second standard cell further comprising a plurality of second nanowires, each connected to the dummy pad and the second dummy pad.
5. The semiconductor integrated circuit device of claim 1 ,
the plurality of nanowires includes a plurality of third nanowires arranged in a third direction perpendicular to a substrate.
6. A semiconductor integrated circuit device, comprising:
a first standard cell including a nanowire field effect transistor (FET) and having a logical function; and
a cell-row-terminating cell disposed adjacent to the first standard cell in a first direction and having no logical function,
wherein
the nanowire FET includes:
a plurality of nanowires extending in the first direction,
a first and second pads that are respectively arranged at both ends of the plurality of nanowires in the first direction, each connected to the plurality of nanowires, and
the cell-row-terminating cell includes a dummy pad having no contribution to a logical function of a circuit.
7. The semiconductor integrated circuit device of claim 6 , wherein
the first pad, the second pad and the dummy pad are arranged at an equal pitch in the first direction.
8. The semiconductor integrated circuit device of claim 6 , wherein
the first pad, the second pad and the dummy pad have an equal pad width as a dimension in the first direction, have an equal pad height as a dimension in a second direction perpendicular to the first direction, and/or have a same position in the second direction.
9. The semiconductor integrated circuit device of claim 6 ,
the cell-row-terminating cell further comprising a second dummy pad, and
the first pad, the second pad, the dummy pad and the second dummy pad are arranged at an equal pitch in the first direction.
10. The semiconductor integrated circuit device of claim 9 ,
the cell-row-terminating cell further comprising a plurality of second nanowires, each connected to the dummy pad and the second dummy pad.
11. The semiconductor integrated circuit device of claim 6 ,
the plurality of nanowires includes a plurality of third nanowires arranged in a third direction perpendicular to a substrate.
12. A semiconductor integrated circuit device, comprising:
a first standard cell including a nanowire field effect transistor (FET) and having a logical function; and
a second standard cell disposed adjacent to the first standard cell in a first direction and having no logical function,
wherein
the nanowire FET includes:
a plurality of nanowires extending in the first direction,
a first and second pads that are respectively arranged at both ends of the plurality of nanowires in the first direction, each connected to the plurality of nanowires, and
the second standard cell includes a dummy pad having no contribution to a logical function of a circuit,
the first and second standard cells are supplied with first and second power supply potentials, and
the dummy pad is supplied with the first power supply potential.
13. The semiconductor integrated circuit device of claim 12 , wherein
the first pad, the second pad and the dummy pad are arranged at an equal pitch in the first direction.
14. The semiconductor integrated circuit device of claim 12 , wherein
the first pad, the second pad and the dummy pad have an equal pad width as a dimension in the first direction, have an equal pad height as a dimension in a second direction perpendicular to the first direction, and/or have a same position in the second direction.
15. The semiconductor integrated circuit device of claim 12 ,
the second standard cell further comprising a second dummy pad, and
the first pad, the second pad, the dummy pad and the second dummy pad are arranged at an equal pitch in the first direction.
16. The semiconductor integrated circuit device of claim 15 , wherein
the second dummy pad is supplied with the first power supply potential.
17. The semiconductor integrated circuit device of claim 15 ,
the second standard cell further comprising a plurality of second nanowires, each connected to the dummy pad and the second dummy pad.
18. The semiconductor integrated circuit device of claim 12 ,
the plurality of nanowires includes a plurality of third nanowires arranged in a third direction perpendicular to a substrate.
19. The semiconductor integrated circuit device of claim 12 , wherein
the second standard cell further comprising a dummy gate line.
20. The semiconductor integrated circuit device of claim 19 , wherein
the dummy gate line is supplied with the first power supply potential.