Bonded three-dimensional memory devices and methods of making the same by replacing carrier substrate with source layer

1. A semiconductor structure comprising a memory die, the memory die comprising:

an alternating stack of insulating layers and electrically conductive layers;

memory stack structures extending through the alternating stack, wherein each of the memory stack structures comprises a respective vertical semiconductor channel and a respective memory film;

drain regions located at a first end of a respective one of the vertical semiconductor channels; and

a source layer having a first surface and a second surface, wherein the first surface is located at a second end of each of the vertical semiconductor channels,

wherein a semiconductor wafer is not located over the second surface of the source layer.

2. The semiconductor structure of claim 1 , further comprising:

a backside dielectric isolation structure comprising a base portion having a horizontal surface and a pedestal portion that protrudes away from the horizontal surface and having a lesser lateral extent than the base portion; and

a first pass-through via structure vertically extending through the base portion of the backside dielectric isolation structure.

3. The semiconductor structure of claim 2 , wherein:

the horizontal surface of the backside dielectric isolation structure contacts a horizontal surface of the alternating stack; and

the source layer contacts the second end of each of the vertical semiconductor channels and contacts the first pass-through via structure.

4. The semiconductor structure of claim 3 , wherein each of the vertical semiconductor channels comprises a cylindrical portion that extends through the alternating stack and a cap portion located at the second end and contacting the source layer.

5. The semiconductor structure of claim 2 , further comprising a pedestal semiconductor portion contacting a horizontal surface of the pedestal portion of the backside dielectric isolation structure.

6. The semiconductor structure of claim 5 , wherein:

a periphery of horizontal surface of the pedestal portion of the backside dielectric isolation structure is coincident with a periphery of a sidewall of the pedestal semiconductor portion; and

the pedestal semiconductor portion comprises a single crystalline semiconductor material.

7. The semiconductor structure of claim 2 , wherein the source layer comprises a polycrystalline or microcrystalline doped semiconductor material.

8. The semiconductor structure of claim 2 , wherein the first pass-through via structure vertically extends through the alternating stack, and wherein the semiconductor structure further comprises a first cylindrical insulating spacer laterally surrounding the first pass-through via structure and vertically extending through the alternating stack and the base portion of the backside dielectric isolation structure.

9. The semiconductor structure of claim 2 , further comprising:

a stepped dielectric material portion contacting the alternating stack; and

a second pass-through via structure vertically extending through the base portion of the backside dielectric isolation structure and through at least one of the alternating stack or the stepped dielectric material portion.

10. The semiconductor structure of claim 9 , further comprising a connection pad contacting the second pass-through via structure and a surface of the base portion of the backside dielectric isolation structure, wherein the connection pad comprise a same doped semiconductor material as the source layer, or comprises a metallic material that is different from a material of the source layer.

11. The semiconductor structure of claim 2 , wherein the source layer contacts peripheral region of the base portion of the backside dielectric isolation structure and does not directly contact the pedestal portion of the backside dielectric isolation structure.

12. The semiconductor structure of claim 1 , wherein each of the memory films comprises a respective annular surface that contacts the source layer.

13. The semiconductor structure of claim 1 , further comprising a logic die bonded to the memory die and comprising a peripheral circuitry configured to operate memory elements in the memory stack structures and to drive the electrically conductive layers.

14. A method of forming a semiconductor structure, comprising:

forming a memory die over a carrier substrate wherein the memory die comprises memory stack structures that vertically extend through an alternating stack of insulating layers and electrically conductive layers, and a first pass-through via structure, wherein each of the memory stack structures comprises a respective vertical semiconductor channel and a respective memory film;

physically exposing a distal end of each of the vertical semiconductor channels and a distal end of the first pass-through via structure; and

forming a source layer directly on a semiconductor material of the distal end of each of the vertical semiconductor channels.

15. The method of claim 14 , further comprising patterning a dielectric isolation layer located on the carrier substrate, wherein a remaining portion of the dielectric isolation layer comprises a backside dielectric isolation structure that includes a base portion contacting a horizontal surface of the alternating stack and a pedestal portion that protrudes away from the horizontal surface and having a lesser lateral extent than the base portion.

16. The method of claim 15 , further comprising:

forming a source-level sacrificial material layer on the dielectric isolation layer, wherein the alternating stack is formed over the source-level sacrificial material layer, and each of the memory films is formed directly on the source-level sacrificial material layer; and

removing the source-level sacrificial material layer after patterning the dielectric isolation layer, wherein end portions of the memory films are physically exposed.

17. The method of claim 16 , further comprising:

forming a recess region in a top portion of the carrier substrate by recessing an area of the dielectric isolation layer;

depositing a source-level sacrificial material within the recess region; and

removing excess portions of the source-level sacrificial material from above a horizontal plane including a top surface of the dielectric isolation layer, wherein a remaining portion of the source-level sacrificial material comprises the source-level sacrificial material layer.

18. The method of claim 15 , wherein:

the source layer comprises an electrically conductive material which is also formed directly on the first pass-through via structure;

the carrier substrate comprises a substrate semiconductor layer;

the dielectric isolation layer is formed on a top surface of the substrate semiconductor layer; and

the method further comprises removing at least a backside portion of the carrier substrate prior to formation of a backside dielectric isolation structure.

19. The method of claim 15 , further comprising:

forming a second pass-through via structure through the alternating stack and into the dielectric isolation layer, wherein a surface of the second pass-through via structure is physically exposed upon patterning of the dielectric isolation layer; and

forming a connection pad on a surface of the second pass-through via structure,

wherein the first pass-through via structure vertically extends through the alternating stack, and is laterally spaced from the alternating stack by a first cylindrical insulating spacer.

20. The method of claim 14 , further comprising:

providing a logic die comprising a peripheral circuitry configured to operate memory elements in the memory stack structures and to drive the electrically conductive layers within the alternating stack; and

bonding the logic die to the memory die.