FinFET structure and method with reduced fin buckling
The present disclosure provides one embodiment of a method making semiconductor structure. The method includes forming a composite stress layer on a semiconductor substrate, wherein the forming of the composite stress layer includes forming a first stress layer of a dielectric material with a first compressive stress and forming a second stress layer of the dielectric material with a second compressive stress on the first stress layer, the second compressive stress being greater than the first compressive stress; and patterning the semiconductor substrate to form fin active regions using the composite stress layer as an etch mask.
1. A semiconductor structure comprising:
a fin active region extruded above a semiconductor substrate;
a gate stack disposed on a top surface and sidewalls of the fin active region, wherein the gate stack includes a gate dielectric layer and a gate electrode; and
a composite stress layer interposed between the top surface of the fin active region and the gate dielectric layer, wherein the composite stress layer includes a first silicon nitride layer and a second silicon nitride layer on the first silicon nitride layer, the first silicon nitride layer having a first compressive stress and the second silicon nitride layer having a second compressive stress greater than the first compressive stress.
2. The semiconductor structure of claim 1 , wherein
the first silicon nitride layer has a first density; and
the second silicon nitride layer has a second density less than the first density.
3. The semiconductor structure of claim 1 , wherein
the first silicon nitride layer has the first compressive stress less than 0.5 GPa; and
the second silicon nitride layer has the second compressive stress greater than 2.5 GPa.
4. The semiconductor structure of claim 3 , wherein
the first compressive stress of the first silicon nitride layer ranges between 0.2 GPa and 0.4 GPa; and
the second compressive stress of the second silicon nitride layer ranges between 2.8 GPa and 3.0 GPa.
5. The semiconductor structure of claim 1 , wherein
the first silicon nitride layer has a first Young's module; and
the second silicon nitride layer has a second Young's module less than the first Young's module.
6. The semiconductor structure of claim 1 , wherein the composite stress layer further includes a first stress layer disposed between the first and second silicon nitride layers, wherein the first stress layer has a tensile stress.
7. The semiconductor structure of claim 6 , wherein the first stress layer includes an amorphous silicon layer having the tensile stress ranging between −0.3 GPa and −0.5 GPa.
8. The semiconductor structure of claim 6 , wherein the composite stress layer further includes a second stress layer disposed between the first stress layer and the second silicon nitride layer, wherein the second stress layer includes silicon carbon nitride.
9. The semiconductor structure of claim 1 , wherein
the composite stress layer is directly disposed on a top surface of the fin active region and is free from sidewalls of the fin active region; and
the gate stack includes a high-k dielectric material and metal.
10. A semiconductor structure comprising:
a fin active region extruded above a semiconductor substrate;
a gate stack disposed on a top surface and sidewalls of the fin active region, wherein the gate stack includes a gate dielectric layer and a gate electrode; and
a composite stress layer interposed between the top surface of the fin active region and the gate dielectric layer, wherein the composite stress layer includes a first stress layer of a dielectric material with a first compressive stress and a second stress layer of the dielectric material with a second compressive stress on the first stress layer, the second compressive stress being greater than the first compressive stress.
11. The semiconductor structure of claim 10 , wherein
the first stress layer has a first density; and
the second stress layer has a second density less than the first density.
12. The semiconductor structure of claim 10 , wherein
the first stress layer has a first Young's module; and
the second stress layer has a second Young's module less than the first Young's module.
13. The semiconductor structure of claim 10 , wherein the dielectric material includes silicon nitride.
14. The semiconductor structure of claim 13 , wherein the composite stress layer further includes a third stress layer disposed between the first and second stress layers, wherein the third stress layer has a tensile stress.
15. The semiconductor structure of claim 14 , wherein
the first stress layer has the first compressive stress less than 0.5 GPa; and
the second stress layer has the second compressive stress greater than 2.5 GPa,
the third stress layer is an amorphous silicon layer having the tensile stress ranging between −0.3 GPa and −0.5 GPa.
16. The semiconductor structure of claim 14 , wherein the composite stress layer further includes a fourth stress layer disposed between the second stress layer and the third stress layer, wherein the fourth stress layer includes silicon carbon nitride.
17. The semiconductor structure of claim 10 , wherein the composite stress layer is directly disposed on a top surface of the fin active region and is free from sidewalls of the fin active region.
18. A semiconductor structure comprising:
a fin active region extruded above a semiconductor substrate;
a gate stack disposed on a top surface and sidewalls of the fin active region, wherein the gate stack includes a gate dielectric layer and a gate electrode; and
a composite stress layer interposed between the top surface of the fin active region and the gate dielectric layer, wherein the composite stress layer includes
a first stress layer of a first compressive stress;
a second stress layer of a second compressive stress on the first stress layer; and
a third stress layer of a tensile stress disposed between the first and second stress layers.
19. The A semiconductor structure of claim 18 , wherein
each of the first and second stress layers includes silicon nitride; and
the third stress layer includes amorphous silicon.
20. The semiconductor structure of claim 19 , wherein the composite stress layer further includes a fourth stress layer disposed between the second stress layer and the third stress layer, wherein the fourth stress layer includes silicon carbon nitride.