High resolution attenuator or phase shifter with weighted bits
Digital step attenuator (DSA) and digital phase shifter (DPS) multi-stage circuit architectures that provide for high resolution. Embodiments use a dithering approach to weight bit positions to provide a much finer resolution than the lowest-valued individual stage. Bit position weights for stages are determined so as to enable selection of combinations of n bit positions that provide a desired total attenuation or phase shift range while allowing utilization of the large number of states (2 n ) available to produce fractional intermediate steps of attenuation or phase shift. The fractional intermediate steps have a resolution finer than the lowest-valued stage. Bit position weights may be determined using a weighting function, including weightings determined from a linear series, a geometric series, a harmonic series, or alternating variants of such series. In some embodiments, at least one bit position has a fixed value that is not determined by the bit position weighting function.
1. An electronic digital step attenuator circuit, including:
(a) multiple series-connected attenuator stages, each attenuator stage being assigned a bit position and being digitally selectable by an associated control line to be in a reference state or in an attenuation state;
(b) wherein each attenuator stage is configured with components to provide an associated value of signal attenuation; and
(c) wherein the associated value of signal attenuation for a plurality of the attenuator stages is a function of a corresponding bit position weight determined by applying a bit position weighting function that produces intermediate steps of signal attenuation having a resolution finer than the signal attenuation value of a lowest-valued attenuator stage.
2. The invention of claim 1 , wherein the bit position weighting function is one of a linear series function or an alternating linear series function or a geometric series function or an alternating geometric series function or a harmonic series function or an alternating harmonic series function.
3. The invention of claim 1 , wherein at least one attenuator stage is configured to have a fixed signal attenuation value.
4. An electronic transmission line digital step attenuator circuit, including:
(a) a transmission line coupled to multiple shunt attenuator stages, each attenuator stage being assigned a bit position and being digitally selectable by an associated control line to be in a reference state or in an attenuation state;
(b) wherein each attenuator stage is configured with components to provide an associated value of signal attenuation; and
(c) wherein the associated value of signal attenuation for a plurality of the attenuator stages is a function of a corresponding bit position weight determined by applying a bit position weighting function that produces intermediate steps of signal attenuation having a resolution finer than the signal attenuation value of a lowest-valued attenuator stage.
5. The invention of claim 4 , wherein the bit position weighting function is one of a linear series function or an alternating linear series function or a geometric series function or an alternating geometric series function or a harmonic series function or an alternating harmonic series function.
6. The invention of claim 4 , wherein at least one attenuator stage is configured to have a fixed signal attenuation value.
7. An electronic transmission line digital phase shifter circuit, including:
(a) a transmission line coupled to multiple shunt phase shifter stages, each phase shifter stage being assigned a bit position and being digitally selectable by an associated control line to be in a reference state or in a phase shift state;
(b) wherein each phase shifter stage is configured with components to provide an associated value of signal phase shift; and
(c) wherein the associated value of signal phase shift for a plurality of phase shifter stages is a function of a corresponding bit position weight determined by applying a bit position weighting function that produces intermediate steps of signal phase shift having a resolution finer than the signal phase shift value of a lowest-valued phase shifter stage.
8. The invention of claim 7 , wherein the bit position weighting function is one of a linear series function or an alternating linear series function or a geometric series function or an alternating geometric series function or a harmonic series function or an alternating harmonic series function.
9. The invention of claim 7 , wherein at least one phase shifter stage is configured to have a fixed signal phase shift value.
10. A method for setting bit position weights for an electronic digital step attenuator circuit that includes multiple series-connected attenuator stages, each attenuator stage being assigned a bit position and being digitally selectable by an associated control line to be in a reference state or in an attenuation state, the method including:
(a) configuring each attenuator stage with components to provide an associated value of signal attenuation; and
(b) setting the associated value of signal attenuation for a plurality of attenuator stages as a function of a corresponding bit position weight determined by applying a bit position weighting function that produces intermediate steps of signal attenuation having a resolution finer than the signal attenuation value of a lowest-valued attenuator phase shifter stage.
11. The method of claim 10 , wherein the bit position weighting function is one of a linear series function or an alternating linear series function or a geometric series function or an alternating geometric series function or a harmonic series function or an alternating harmonic series function.
12. The method of claim 10 , further including setting the associated value of signal attenuation for at least one attenuator stage to a fixed value.
13. A method for setting bit position weights for an electronic transmission line digital step attenuator circuit that includes multiple shunt attenuator stages, each attenuator stage being assigned a bit position and being digitally selectable by an associated control line to be in a reference state or in an attenuation state, the method including:
(a) configuring each attenuator stage with components to provide an associated value of signal attenuation; and
(b) setting the associated value of signal attenuation for a plurality of attenuator stages as a function of a corresponding bit position weight determined by applying a bit position weighting function that produces intermediate steps of signal attenuation having a resolution finer than the signal attenuation value of a lowest-valued attenuator stage.
14. The method of claim 13 , wherein the bit position weighting function is one of a linear series function or an alternating linear series function or a geometric series function or an alternating geometric series function or a harmonic series function or an alternating harmonic series function.
15. The method of claim 13 , further including setting the associated value of signal attenuation for at least one attenuator stage to a fixed value.
16. A method for setting bit position weights for an electronic transmission line digital phase shifter circuit that includes multiple shunt phase shifter stages, each phase shifter stage being assigned a bit position and being digitally selectable by an associated control line to be in a reference state or in a phase shift state, the method including:
(a) configuring each phase shifter stage with components to provide an associated value of signal phase shift; and
(b) setting the associated value of signal phase shift for a plurality of phase shifter stages as a function of a corresponding bit position weight determined by applying a bit position weighting function that produces intermediate steps of signal phase shift having a resolution finer than the signal phase shift value of a lowest-valued phase shifter stage.
17. The method of claim 16 , wherein the bit position weighting function is one of a linear series function or an alternating linear series function or a geometric series function or an alternating geometric series function or a harmonic series function or an alternating harmonic series function.
18. The method of claim 16 , further including setting the associated value of signal phase shift for at least one phase shifter stage to a fixed value.