High resolution attenuator or phase shifter with weighted bits
Digital step attenuator (DSA) and digital phase shifter (DPS) multi-stage circuit architectures that provide for high resolution. Embodiments use a dithering approach to weight bit positions to provide a much finer resolution than the lowest-valued individual stage. Bit position weights for stages are determined so as to enable selection of combinations of n bit positions that provide a desired total attenuation or phase shift range while allowing utilization of the large number of states (2 n ) available to produce fractional intermediate steps of attenuation or phase shift. The fractional intermediate steps have a resolution finer than the lowest-valued stage. Bit position weights may be determined using a weighting function, including weightings determined from a linear series, a geometric series, a harmonic series, or alternating variants of such series. In some embodiments, at least one bit position has a fixed value that is not determined by the bit position weighting function.
1 . An electronic circuit, including:
(a) multiple stages, each stage configured to selectively alter the attenuation or phase of an applied signal, each stage having an input port and an output port, each stage being assigned one of N bit positions where N is greater than or equal to 1, each stage being digitally selectable by an associated control line to be either in a reference state in which a received input signal applied at the input port is conducted to the output port, or in an active signal alteration state;
(b) wherein each stage is configured to provide a value of signal alteration;
(c) wherein the value of signal alteration for each stage assigned a bit position has a weight set by application of a weighting function; and
(d) wherein the multiple stages enable selection of 2 N combinations of stages to provide a total range of signal alteration, the total range of signal alteration having a smallest level of signal alteration and a largest level of signal alteration, and to provide multiple levels of signal alteration within the total range of signal alteration between the smallest and the largest levels of signal alteration, wherein each of the multiple levels of signal alteration has a resolution less than the value of signal alteration of any one stage of the multiple stages.
2 . The electronic circuit of claim 1 , further including a selector coupled to the control line of each of the multiple stages and configured to decode a supplied control word into the control lines, wherein the selector enables selection of the 2 N combinations of stages.
3 . The electronic circuit of claim 1 , wherein the weighting function is selected from the group consisting of:
(a) a linear series function, wherein an n th bit weighting value of the N bit positions equals A0+(n−1)×K) or equals A0−((n−1)×K; and
(b) an alternating linear series function, wherein an n th bit weighting value of the N bit positions equals A0+(−1) n ×((n−1)×K) or equals A0+(−1) (n-1) ×((n−1)×K);
wherein A0 is a constant, n is the bit position of a stage and is greater than or equal to one, and K is a non-zero proportionality constant.
4 . The electronic circuit of claim 1 , wherein the weighting function is selected from the group consisting of:
(a) a geometric series function, wherein an n th bit weighting value of the N bit positions equals A0+K/2 (n-1) or equals A0−K/2 (n-1) ; and
(b) an alternating geometric series function, wherein an n th bit weighting value of the N bit positions equals A0+(−1) (n-1) ×K/2 (n-1) or equals A0+(−1) n ×K/2 (n-1) ;
wherein A0 is a constant, n is the bit position of a stage and is greater than or equal to one, and K is a non-zero proportionality constant.
5 . The electronic circuit of claim 1 , wherein the weighting function is selected from the group consisting of:
(a) a harmonic series function, wherein an n th bit weighting value of the N bit positions equals A0+K/n or equals A0−K/n; and
(b) an alternating harmonic series function, wherein an n th bit weighting value of the N bit positions equals A0+(−1) n ×K/n or equals A0+(−1) (n-1) ×K/n;
wherein A0 is a constant, n is the bit position of a stage and is greater than or equal to one, and K is a non-zero proportionality constant.
6 . The electronic circuit of any of claim 1 , further including at least one stage having a signal alteration value set to a fixed value not determined by the weighting function.
7 . The electronic circuit of claim 1 , wherein the multiple stages include multiple series-connected attenuator stages configured as an electronic digital step attenuator circuit.
8 . The electronic circuit of claim 7 , further including at least one series-connected attenuator stage having a signal attenuation value set to a fixed value not determined by the alternating harmonic series weighting function.
9 . The electronic circuit of claim 1 , wherein the multiple stages include multiple shunt attenuator stages coupled to a transmission line and configured as an electronic digital step attenuator circuit.
10 . The electronic circuit of claim 1 , wherein the multiple stages include multiple shunt phase shifter stages coupled to a transmission line and configured as an electronic digital phase shifter circuit.
11 . A method for setting a value of signal alteration per stage for multiple stages of an electronic circuit and selecting a level of signal alteration within a total range of signal alteration enabled by the multiple stages, each stage having an input port and an output port, each stage configured to selectively alter the attenuation or phase of a signal applied to the input port, each stage being assigned one of N bit positions where N is greater than or equal to 1, each stage being digitally selectable by an associated control line to be either in a reference state in which the signal applied at the input port is conducted to the output port, or in an active signal alteration state, the method including:
(a) configuring each stage to provide a value of signal alteration;
(b) setting the value of signal alteration for each stage to a weight set by application of a weighting function;
(c) selecting any of 2 N combinations of stages to provide a level of signal alteration within the total range of signal alteration, the total range of signal alteration having a smallest level of signal alteration and a largest level of signal alteration, and to provide multiple levels of signal alteration within the total range of signal alteration between the smallest and the largest levels of signal alteration, wherein each of the multiple levels of signal alteration has a resolution less than the value of signal alteration of any one stage of the multiple stages.
12 . The method of claim 11 , further including providing a selector coupled to the control line of each of the multiple stages and configuring the selector to decode a supplied control word into the control lines, wherein the selector enables selection of the 2 N combinations of stages.
13 . The method of claim 11 , wherein the bit position weighting function is selected from the group consisting of:
(a) a linear series function, wherein an n th bit weighting value of the N bit positions equals A0+((n−1)×K) or equals A0−((n−1)×K; and
(b) an alternating linear series function, wherein an n th bit weighting value of the N bit positions equals A0+(−1) n ×((n−1)×K) or equals A0+(−1) (n-1) ×((n−1)×K);
wherein A0 is a constant, n is the bit position of a stage and is greater than or equal to one, and K is a non-zero proportionality constant.
14 . The method of claim 11 , wherein the bit position weighting function is selected from the group consisting of:
(a) a geometric series function, wherein an n th bit weighting value of the N bit positions equals A0+K/2 (n-1) or equals A0−K/2 (n-1) ; and
(b) an alternating geometric series function, wherein an n th bit weighting value of the N bit positions equals A0+(−1) (n-1) ×K/2 (n-1) or equals A0+(−1) n ×K/2 (n-1) ;
wherein A0 is a constant, n is the bit position of a stage and is greater than or equal to one, and K is a non-zero proportionality constant.
15 . The method of claim 11 , wherein the bit position weighting function is selected from the group consisting of:
(a) a harmonic series function, wherein an n th bit weighting value of the N bit positions equals A0+K/n or equals A0−K/n; and
(b) an alternating harmonic series function, wherein an n th bit weighting value of the N bit positions equals A0+(−1) n ×K/n or equals A0+(−1) (n-1) ×K/n;
wherein A0 is a constant, n is the bit position of a stage and is greater than or equal to one, and K is a non-zero proportionality constant.
16 . The method of any of claim 11 , further including providing at least one stage having a signal alteration value set to a fixed value not determined by the weighting function.
17 . The method of claim 11 , wherein the multiple stages include multiple series-connected attenuator stages configured as an electronic digital step attenuator circuit.
18 . The method of claim 17 , wherein the multiple stages include at least one series-connected attenuator stage having a signal attenuation value set to a fixed value not determined by the alternating harmonic series weighting function.
19 . The method of claim 11 , wherein the multiple stages include multiple shunt attenuator stages coupled to a transmission line and configured as an electronic digital step attenuator circuit.
20 . The method of claim 11 , wherein the multiple stages include multiple shunt phase shifter stages coupled to a transmission line and configured as an electronic digital phase shifter circuit.