System and methods for mixed-signal computing
A mixed-signal integrated circuit that includes: a global reference signal source; a first summation node and a second summation node; a plurality of distinct pairs of current generating circuits arranged along the first summation node and the second summation node; a first current generating circuit of each of the plurality of distinct pairs that is arranged on the first summation node and a second current generating circuit of each of the plurality of distinct pairs is arranged on the second summation node; a common-mode current circuit that is arranged in electrical communication with each of the first and second summation nodes; where a local DAC adjusts a differential current between the first second summation nodes based on reference signals from the global reference source; and a comparator or a finite state machine that generates a binary output value current values obtained from the first and second summation nodes.
1. An integrated circuit comprising:
a signal source that sources one or more signals to a plurality of signal sources, wherein a distinct one signal source of the plurality of signal sources is arranged in electrical communication with one or more electrical conduits;
a circuit that:
(i) identifies current values along the one or more electrical conduits; and
(ii) computes a binary output value based on the current values along the one or more electrical conduits; and
an integrator that sums the one or more signals based on the binary output value.
2. The integrated circuit according to claim 1 , wherein
the distinct one signal source includes an integrator circuit that sums the one or more signals based on an input of the binary output value.
3. The integrated circuit according to claim 1 , further comprising:
an integrator that increments or decrements a charge on a capacitor or a storage device based on the binary output value.
4. The integrated circuit according to claim 1 , wherein
the distinct one signal source comprises a digital-to-analog converter (DAC); and
the binary output signal comprises a biasing input signal to the DAC causing an increasing or decreasing summation of the one or more signals.
5. The integrated circuit according to claim 1 , wherein
the signal source sources a plurality of signals to each of the plurality of signal sources, and
a summation of the plurality of signals to each of the plurality of signal sources is based on the binary output value.
6. The integrated circuit according to claim 1 , wherein:
the one distinct signal source includes an integrator that accumulates multiple input signals from the signal source based on the binary output value biasing the integrator.
7. The integrated circuit according to claim 1 , wherein
the signal source sources a plurality of signals to the plurality of signal sources,
each of the plurality of signal sources sums the plurality of signals over a period based on the binary output value, and
each of the plurality of signal sources outputs a single analog signal to the one or more electrical conduits based on the sum.
8. The integrated circuit according to claim 1 , wherein
the circuit comprises:
a control circuit that sources to or sinks from each electrical conduit of the one or more electrical conduits an analog signal value; and
sets a target condition between the one or more electrical conduits based on the analog signal value.
9. The integrated circuit according to claim 8 , wherein
the control circuit generates the electrical current value based on a measured voltage value of the one or more electrical conduits.
10. The integrated circuit according to claim 1 , wherein
the circuit comprises:
comparator circuitry that evaluates analog values based on outputs of the one or more electrical conduits and generates the binary output value based on the evaluation.
11. The integrated circuit according to claim 10 , wherein
the evaluation by the comparator circuitry includes:
assessing a relative state of a summed current value in each of a first electrical conduit and of a second electrical conduit of the one or more electrical conduits, and
determining which of the first electrical conduit and the second electrical conduit has a larger summed current value or a smaller summed current value.
12. The integrated circuit according to claim 1 , wherein
the circuit comprises:
a finite state machine that evaluates analog values based on outputs of the one or more electrical conduits and generates the binary output value based on the evaluation.
13. The integrated circuit according to claim 1 , further comprising:
multiple distinct pairs of tunable resistors;
multiple pairs of electrical conduits, wherein:
each of the multiple distinct pairs of tunable resistors is arranged along one pair of the multiple pairs of electrical conduits, and
the circuit comprises an analog multiplexor that is arranged in electrical communication with each of the multiple pairs of electrical conduits.
14. The integrated circuit according to claim 1 , further comprising:
multiple distinct pairs of tunable resistors;
multiple pairs of electrical conduits, wherein:
each of the multiple distinct pairs of tunable resistors is arranged along one pair of the multiple pairs of electrical conduits,
the distinct one signal source of the plurality of signal sources is arranged in electrical communication with each of the multiple pairs of electrical conduits.
15. The integrated circuit according to claim 14 , wherein
the distinct one signal source sources a signal to each of the multiple pairs of electrical conduits based on the one or more signals from the signal source.
16. The integrated circuit according to claim 1 , wherein
the circuit changes a differential current value between the one or more electrical conduits until a summation of an output of a first analog signal value of a first electrical conduit and a second analog signal value of a second electrical conduit of the one or more electrical conduits satisfy a predetermined condition.
17. The integrated circuit according to claim 1 , wherein
the circuit increases or decreases a differential analog signal between the one or more electrical conduits by sourcing to one of a first electrical conduit and a second electrical conduit of the one or more electrical conduits a progressively smaller differential analog signal increment based on which of the first electrical conduit and the second electrical conduit that outputs an analog signal value with a higher magnitude.
18. The integrated circuit according to claim 1 , wherein
the signal source executes a binary search algorithm such that at each step of the binary search algorithm, the signal source sets a binary-weighted value with which each of the plurality of signal sources to adjust a respective local state of each of the plurality of signal sources.
19. The integrated circuit according to claim 1 , wherein
the signal source executes one of a least significant bit search algorithm, a non-binary search algorithm, a logarithmic search algorithm, and a custom user-defined search function.
20. An integrated circuit comprising:
a signal source that sources one or more signals to a plurality of signal sources, wherein a distinct one signal source of the plurality of signal sources is arranged in electrical communication with one or more electrical conduits;
a circuit that:
(i) identifies current values along the one or more electrical conduits; and
(ii) computes a binary output value based on the current values along the one or more electrical conduits; and
an integrator that increments or decrements a charge on a capacitor or a storage device based on the binary output value.
21. An integrated circuit comprising:
a signal source that sources one or more signals to a plurality of signal sources, wherein a distinct one signal source of the plurality of signal sources is arranged in electrical communication with one or more electrical conduits;
a circuit that:
(i) identifies current values along the one or more electrical conduits; and
(ii) computes a binary output value based on the current values along the one or more electrical conduits,
wherein the distinct one signal source comprises a digital-to-analog converter (DAC); and
the binary output signal comprises a biasing input signal to the DAC causing an increasing or decreasing summation of the one or more signals.