IP Library › Granted Patent US 11,416,154
Granted Patent B2
US 11,416,154 · App. 17/123,472 · Granted Aug 16, 2022

Partially written block treatment

Inventors: Sivagnanam Parthasarathy (Carlsbad, CA); Terry M. Grunzke (Boise, ID); Lucia Botticchio (Pescina, IT); Walter Di Francesco (Avezzano, IT); Vamshi K. Indavarapu (San Jose, CA); Gianfranco Valeri (Pescina, IT); Renato C. Padilla (Folsom, CA); Ali Mohammadzadeh (Mountain View, CA); Jung Sheng Hoei (Newark, CA); Luca De Santis (Avezzano, IT)
Assignee: Micron Technology, Inc.
G06F3/064G06F3/0611G06F3/0659G06F3/0679G06F3/0688G06F12/0246G06F12/1009G06F2212/1021G06F2212/2022G06F2212/7201
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Quick Facts
Patent No.
US 11,416,154
App. No.
17/123,472
Granted
Aug 16, 2022
Kind
B2
Abstract

The present disclosure relates to partially written block treatment. An example method comprises maintaining, internal to a memory device, a status of a last written page corresponding to a partially written block. Responsive to receiving, from a controller, a read request to a page of the partially written block, the example method can include determining, from page map information maintained internal to the memory device and from the status of the last written page, which of a number of different read trim sets to use to read the page of the partially written block corresponding to the read request.

Claims (44)

1. An apparatus, comprising:

a controller internal to a memory device configured to:

maintain a status of a last written page corresponding to a partially written block; and

determine, from page map information and the status of the last written page, a read trim set to use to read a page of the partially written block,

wherein the controller is not responsible for logical to physical address translation for the memory device.

2. The apparatus of claim 1 , wherein the memory device is a component of a solid state drive (SSD) and is coupled to a system controller of the SSD via a bus.

3. The apparatus of claim 2 , wherein the bus is associated with an Open NAND Flash Interface (ONFI) structure.

4. The apparatus of claim 1 , wherein the page map information includes a page programming order.

5. The apparatus of claim 1 , wherein the status of the last written page includes a page number, and

wherein the controller is configured to determine a location of the page relative to the last written page based on the page programming order.

6. The apparatus of claim 1 , wherein the status of the last written page corresponding to the partially written block includes a page identifier and an indication as to an amount of programming of the last written page.

7. A method comprising:

maintaining a status of a last written page and page map information corresponding to a partially written block with a controller internal to a memory device; and

determining, with the controller without interaction with a system controller that is responsible for logical to physical address translation for the memory device, a read trim set to use to read a page of the partially written block from the page map information and the status of the last written page.

8. The method of claim 7 , further comprising providing a read request for the page of the partially written block to the memory device without communicating to the system controller that the read request corresponds to the partially written block.

9. The method of claim 8 , wherein providing the read request comprises providing a block identifier and a page identifier to the memory device.

10. The method of claim 8 , further comprising providing the read request to the memory device responsive to a host-initiated read request corresponding to a particular logical block address.

11. The method of claim 7 , wherein the status of the last written page includes a page number corresponding to the last written page, and

wherein the page map information includes a programming order of pages written to the partially written block.

12. The method of claim 7 , wherein determining the read trim set comprises determining at least one of:

whether memory cells to which the page is written are fully programmed; and

a programming status of memory cells coupled to an access line adjacent to an access line to which the page is written.

13. The method of claim 7 , further comprising performing a read of the page of the partially written block using the determined read trim set without interaction with the system controller.

14. The method of claim 7 , wherein maintaining the page map information comprises maintaining page map information corresponding to a number of different programming process page mappings including at least two different two-pass programming process page mappings.

15. The method of claim 7 , further comprising:

receiving, from the system controller, a write command to the memory device, wherein execution of the write command results in the partially written block;

maintaining with the controller an indication of the partially written block;

receiving, from the system controller, a read request for the partially written block, wherein the read request includes a block identifier and a page identifier;

comparing the block identifier to the indication of the partially written block; and

responsive to determining that the block identifier matches the indication of the partially written block, determining the read trim set.

16. A system, comprising:

a host;

a system controller coupled to the host and configured to perform logical to physical address translation; and

a memory device coupled to the system controller and comprising:

a plurality of blocks configured to store pages of data; and

a controller,

wherein the host is configured to a provide, to the memory device, a read request for a partially written block of the memory device, and

wherein the controller is configured to:

maintain a status of last written pages corresponding to partially written blocks and page map information corresponding to partially written blocks; and

responsive to the read request, select a read trim set to read a page of data of the partially written block based on the status of the last written page and page map information corresponding to the partially written block without interaction with the system controller.

17. The system of claim 16 , wherein the controller is configured to receive the read request for the partially written block from the system controller.

18. The system of claim 16 , wherein the read request includes a block identifier and a page identifier.

19. The system of claim 17 , wherein the system controller is unaware of whether a block identifier of the read request corresponds to the partially written block when providing the read request.

20. The system of claim 16 , wherein the page map information includes page maps corresponding to at least two different two-pass programming processes.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 16, 2020
From: PARTHASARATHY, SIVAGNANAM; GRUNZKE, TERRY M.; INDAVARAPU, VAMSHI K.; PADILLA, RENATO C.; MOHAMMADZADEH, ALI; HOEI, JUNG SHENG; DE SANTIS, LUCA; VALERI, GIANFRANCO; BOTTICCHIO, LUCIA; DI FRANCESCO, WALTER
To: MICRON TECHNOLOGY, INC.
Reel/Frame 054665/0952 →
Continuity (3)
Continuation 16428011 · May 31, 2019
Continuation 15532886
Related Publication 20210103389A1 · Apr 8, 2021
Cited By (1)
US 12,253,957