Granted Patent B2

US 12,253,957 · App. 18/102,779 · Granted Mar 18, 2025

Inventor: Tzu-Yi Yang (Hsinchu County, TW)

Assignee: Silicon Motion, Inc.

G06F12/12G06F12/1009

Abstract

Claims (44)

1. A method of handling trim commands in a flash memory, comprising:

receiving a trim command;

modifying logical-to-physical (L2P) address mapping entries of a L2P address mapping table according to the trim command;

storing trim information of the trim command into one of data blocks of the flash memory without saving the modified L2P address mapping entries to the flash memory after modifying the L2P address mapping entries according to the trim command; and

returning a finish notification to a host device which issues the trim command after storing the trim information into the flash memory.

2. The method of claim 1 , further comprising:

loading the trim information from the flash memory in response to an unintentional power off event; and

modifying L2P address mapping entries of the L2P address mapping table according to the loaded trim information.

3. The method of claim 1 , further comprising:

re-calculating a valid page count of at least one physical block according to the trim command.

4. The method of claim 1 , wherein the step of modifying the L2P address mapping table according to the trim command comprises:

determining a trim range according to a start logical block address and a trim length of at least one trim entry included the trim command; and

modify at least one L2P address mapping entry of the L2P address mapping table if the at least one L2P address mapping entry corresponds to a logical block address within the trim range.

5. The method of claim 1 , wherein the trim information includes a start logical block address and a trim length of each trim entry of the trim command.

6. A memory controller for use in a flash memory to control the flash memory and handle trim commands in the flash memory, comprising:

a storage unit, arranged to store information and program codes;

a processing unit, operable to execute the program codes to be arranged to:

receive a trim command;

modify logical-to-physical (L2P) address mapping entries of a L2P address mapping table according to the trim command;

store trim information of the trim command into one of data blocks of the flash memory without saving the modified L2P address mapping entries to the flash memory after modifying the L2P address mapping entries according to the trim command; and

return a finish notification to a host device which issues the trim command after storing the trim information into the flash memory.

7. The memory controller of claim 6 , wherein the processing unit is arranged to:

load the trim information from the flash memory in response to an unintentional power off event; and

modify L2P address mapping entries of the L2P address mapping table according to the loaded trim information.

8. The memory controller of claim 6 , wherein the processing unit is arranged to:

re-calculate a valid page count of at least one physical block according to the trim command.

9. The memory controller of claim 6 , wherein the processing unit is arranged to:

determine a trim range according to a start logical block address and a trim length of at least one trim entry included the trim command; and

modify at least one L2P address mapping entry of the L2P address mapping table if the at least one L2P address mapping entry correspond to a logical block address within the trim range.

10. The memory controller of claim 6 , wherein the trim information includes a start logical block address and a trim length of each trim entry of the trim command.

11. A storage system comprising a flash memory and the memory controller of claim 6 .

12. A method of handling trim commands in a flash memory, comprising:

receiving a trim command;

modifying logical-to-physical (L2P) address mapping entries of a L2P address mapping table according to the trim command; and

storing trim information of the trim command into one of data blocks of the flash memory after modifying the L2P address mapping entries according to the trim command; and

not selecting the data block that the trim information is stored to as a source block of a garbage collection operation before the modified L2P address mapping entries regarding the trim command have been saved to the flash memory.

13. A memory controller for use in a flash memory to control the flash memory and handle trim commands in the flash memory, comprising:

a storage unit, arranged to store information and program codes;

a processing unit, operable to execute the program codes to be arranged to:

receive a trim command;

modify logical-to-physical (L2P) address mapping entries of a L2P address mapping table according to the trim command;

store trim information of the trim command into one of data blocks of the flash memory after modifying the L2P address mapping entries according to the trim command; and

not to select the data block that the trim information is stored to as a source block of a garbage collection operation before the modified L2P address mapping entries regarding the trim command have been saved to the flash memory.

14. A storage system comprising a flash memory and the memory controller of claim 13 .

Assignments (1)

Continuity (1)

References Cited (10)