IP Library Granted Patent US 12,211,775
Granted Patent B2
US 12,211,775 · App. 17/126,433 · Granted Jan 28, 2025

Multiple substrate package systems and related methods

Inventors: Atapol Prajuckamol (Thanyaburi, TH); Chee Hiong Chew (Seremban, MY); Yusheng Lin (Phoenix, AZ)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L23/49811H01L21/4803H01L21/4842H01L21/4853H01L23/3107H01L23/49833H01L23/5385H01L25/18H01L23/24
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Quick Facts
Patent No.
US 12,211,775
App. No.
17/126,433
Granted
Jan 28, 2025
Kind
B2
Abstract

Implementations of a semiconductor package may include a first substrate including a first group of leads physically coupled thereto and a second group of leads physically coupled thereto; a second substrate coupled over the first substrate and physically coupled to the first group of leads and the second group of leads; and one or more semiconductor die coupled between the first substrate and the second substrate. The second group of leads may be electrically isolated from the first substrate.

Claims (36)

1. A semiconductor package comprising:

a first substrate comprising a first group of leads physically coupled thereto and a second group of leads physically coupled thereto;

a second substrate coupled over the first substrate and physically coupled to the first group of leads and the second group of leads; and

one or more semiconductor die coupled between the first substrate and the second substrate;

wherein the second group of leads is electrically isolated from the first substrate;

wherein the first group of leads is electrically coupled to the one or more semiconductor die through the first substrate;

wherein each lead of the first group of leads and each lead of the second group of leads are coupled between the first substrate and the second substrate; and

wherein the first group of leads and the second group of leads are configured to couple the semiconductor package to an external device.

2. The package of claim 1 , wherein the second group of leads are each coupled to a corresponding electrically isolated copper island formed in a layer of copper on the first substrate.

3. The package of claim 1 , further comprising an encapsulant in a space between the first substrate and the second substrate.

4. The package of claim 1 , wherein the first group of leads and the second group of leads are both coupled on a same side of the first substrate and on a same side of the second substrate.

5. The package of claim 1 , wherein the first group of leads and the second group of leads are coupled on different sides of the first substrate and the second substrate.

6. The package of claim 1 , further comprising one or more leads physically and electrically coupled to the first substrate and to the second substrate.

7. The package of claim 1 , wherein an end of each lead of the first group of leads and an end of each lead of the second group of leads is coined.

8. The package of claim 1 , further comprising a pre-mold encapsulant formed around the first group of leads and the second group of leads.

9. A semiconductor package comprising:

a first substrate comprising a first group of leads physically coupled thereto and a second group of leads physically coupled thereto, the second group of leads physically coupled to corresponding electrically isolated islands coupled one of in or on the first substrate;

a second substrate coupled over the first substrate and physically coupled to the first group of leads and the second group of leads; and

one or more semiconductor die coupled between the first substrate and the second substrate:

wherein the first group of leads and the second group of leads are configured to couple the semiconductor package to an external device.

10. The package of claim 9 , wherein the corresponding electrically isolated islands are comprised in the first substrate.

11. The package of claim 9 , wherein the first group of leads and the second group of leads are both coupled on a same side of the first substrate and on a same side of the second substrate.

12. The package of claim 9 , wherein the first group of leads and the second group of leads are coupled on different sides of the first substrate and the second substrate.

13. The package of claim 9 , further comprising one or more leads physically and electrically coupled to the first substrate and to the second substrate.

14. The package of claim 9 , wherein an end of each lead of the first group of leads and an end of each lead of the second group of leads is coined.

15. The package of claim 9 , further comprising a pre-mold encapsulant formed around the first group of leads and the second group of leads.

16. A method of forming a semiconductor package, the method comprising:

physically and electrically coupling a first group of leads to a first substrate;

physically coupling a second group of leads to the first substrate using corresponding electrically isolated islands coupled one of in or on the first substrate;

physically and electrically coupling a second substrate to the first group of leads and to the second group of leads; and

coupling one or more semiconductor die between the first substrate and the second substrate;

wherein the first group of leads and the second group of leads are configured to couple the semiconductor package to an external device.

17. The method of claim 16 , further comprising coining the first group of leads and the second group of leads.

18. The method of claim 16 , further comprising applying a pre-mold encapsulant around the first group of leads and around the second group of leads.

19. A method of claim 16 , wherein the corresponding electrically isolated islands are comprised in the first substrate.

20. The method of claim 16 , wherein the first group of leads and the second group of leads are coupled on one of a same side of the first substrate or different sides of the first substrate.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL 055315, FRAME 0350 Recorded Aug 17, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064618/0881 →
SECURITY INTEREST Recorded Feb 17, 2021
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 055315/0350 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2020
From: PRAJUCKAMOL, ATAPOL; CHEW, CHEE HIONG; LIN, YUSHENG
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 054691/0462 →