Neuromorphic memory device and method
Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a stack of memory dies, a controller die, and a buffer. Example memory devices, systems and methods include one or more neuromorphic layers logically coupled between one or more dies in the stack of memory dies and a host interface of the controller die.
1. A memory system, comprising:
a controller die coupled to a substrate, the controller die including a buffer, the buffer including a host interface and a die stack interface, wherein the host interface includes at least one channel, and the die stack interface includes two or more sub-channels;
a stack of memory dies supported by the substrate and coupled to the two or more sub-channels, and circuitry in the controller die, configured to operate the host interface at a first data speed, and to operate the two or more sub-channels coupled to the stack of memory dies at a second data speed, slower than the first data speed;
control logic reallocating the connections for the at least one channel to at least two sub-channels; and
one or more neuromorphic layers logically coupled between one or more dies in the stack of dies and the host interface.
2. The memory system of claim 1 , wherein the one or more neuromorphic layers are physically located within the controller die.
3. The memory system of claim 1 , wherein the buffer is configured to control data speed to the one or more neuromorphic layers.
4. The memory system of claim 1 , wherein the one or more neuromorphic layers include digital neuromorphic layers.
5. The memory system of claim 1 , wherein the one or more neuromorphic layers include analog multiply accumulator (MAC) neuromorphic layers.
6. The memory system of claim 1 , wherein the one or more neuromorphic layers include both digital and analog portions.
7. The memory system of claim 1 , wherein the stack of memory dies include DRAM dies.
8. The memory system of claim 1 , wherein the one or more neuromorphic layers include phase change cells.
9. The memory system of claim 1 , wherein the one or more neuromorphic layers include memristor cells.
10. The memory system of claim 1 , wherein the substrate is a motherboard.
11. The memory system of claim 1 , wherein the substrate is a dual in line memory (DIMM) substrate.
12. The memory system of claim 1 , wherein the substrate is an intermediate substrate coupled to a motherboard.
13. A memory system, comprising:
a controller die coupled to a substrate, the controller die including a buffer, the buffer including a host interface and a die stack interface, wherein the host interface includes at least one channel, and the die stack interface includes two or more sub-channels;
a stack of memory dies supported by the substrate and coupled to the two or more sub-channels, and circuitry in the controller die, configured to operate the host interface at a first data speed, and to operate the two or more sub-channels coupled to the stack of memory dies at a second data speed, slower than the first data speed;
control logic reallocating the connections for the at least one channel to at least two sub-channels; and
one or more neuromorphic layers logically coupled between one or more dies in the stack of dies and the host interface; and
logic in the controller die to program one or more neuromorphic weights into the one or more neuromorphic layers.
14. The memory system of claim 13 , wherein the one or more neuromorphic layers are physically located within the controller die.
15. The memory system of claim 13 , wherein the buffer is configured to control data speed to the one or more neuromorphic layers.
16. The memory system of claim 13 , wherein the one or more neuromorphic layers includes multiple layers in a single die.
17. The memory system of claim 13 , wherein the one or more neuromorphic layers includes multiple layers in multiple dies.
18. The memory system of claim 13 , wherein the stack of dies supported by the substrate include one or more wirebond connections to the substrate.
19. The memory system of claim 13 , wherein the stack of dies supported by the substrate include one or more through silicon via (TSV) connections to the substrate.
20. The memory system of claim 13 , wherein the one or more neuromorphic layers includes from 30 to 100 neuromorphic layers.
21. The memory system of claim 13 , wherein multiple memory die stacks are included on a dual in line memory (DIMM) substrate.
22. The memory system of claim 21 , wherein each memory die stack in the multiple die stacks is associated with a separate controller die.
23. A method, comprising
training a neuromorphic device that is located in a memory device;
transferring data from one or more memory dies in a die stack in the memory system to the neuromorphic device at a first data speed;
locally processing the data from the die stack using the neuromorphic device;
transferring the processed data to a host device through a buffer located in the memory system wherein the buffer is configured to provide a second data speed faster than the first data speed.
24. The method of claim 23 , wherein transferring data from one or more memory dies in a die stack in the memory system to the neuromorphic device includes transferring data from one or more memory dies to a neuromorphic device located within the die stack.
25. The method of claim 23 , wherein transferring data from one or more memory dies in a die stack in the memory system to the neuromorphic device includes transferring data from the one or more memory dies to a controller die that includes both the neuromorphic device and the buffer.