Granted Patent B2

US 12,639,236 · App. 18/630,400 · Granted May 26, 2026

Inventors: Brent Keeth (Boise, ID); Frank F Ross (Boise, ID); Richard C Murphy (Boise, ID)

Assignee: Micron Technology, Inc.

G06F13/1668G06N3/004H10W90/00H10W90/24H10W90/297H10W90/752H10W90/754

Abstract

Claims (27)

1 . A memory system, comprising:

a controller die coupled to a substrate, the controller die including a buffer, the buffer including a host interface and a die stack interface, wherein the host interface includes multiple memory channels, wherein a memory channel within the multiple memory channels is dedicated to to two or more sub-channels of the die stack interface to provide memory bandwidth, wherein a ratio of stack interface speed to host interface speed corresponds to a ratio of a number of sub- channels to a number of memory channels;

a stack of memory dies supported by the substrate and coupled to the two or more sub- channels; and

one or more neuromorphic layers logically coupled between one or more dies in the stack of dies and the host interface.

2 . The memory system of claim 1 , wherein the one or more neuromorphic layers are physically located within the controller die.

3 . The memory system of claim 1 , wherein the one or more neuromorphic layers include digital neuromorphic layers.

4 . The memory system of claim 1 , wherein the one or more neuromorphic layers include analog multiply accumulator (MAC) neuromorphic layers.

5 . The memory system of claim 1 , wherein the one or more neuromorphic layers include both digital and analog portions.

6 . The memory system of claim 1 , wherein the stack of memory dies include DRAM dies.

7 . The memory system of claim 1 , wherein the one or more neuromorphic layers include phase change cells.

8 . The memory system of claim 1 , wherein the one or more neuromorphic layers include memristor cells.

9 . The memory system of claim 1 , wherein the memory channel within the multiple memory channels is dedicated to two sub-channels of the die stack interface.

10 . The memory system of claim 1 , wherein the memory channel within the multiple memory channels is dedicated to four sub-channels of the die stack interface.

11 . The memory system of claim 1 , wherein each sub-channel is mapped to multiple dies in the stack of memory dies.

12 . The memory system of claim 1 , wherein each sub-channel is mapped to a single die in the stack of memory dies.

13 . A memory system, comprising:

a controller die coupled to a substrate, the controller die including a buffer, the buffer including a host interface and a die stack interface, wherein the host interface includes multiple memory channels, wherein a memory channel within the multiple memory channels is dedicated to to two or more sub-channels of the die stack interface to provide memory bandwidth, wherein a ratio of stack interface speed to host interface speed corresponds to a ratio of a number of sub-channels to a number of memory channels;

a stack of memory dies supported by the substrate and coupled to the two or more sub-channels;

one or more neuromorphic layers logically coupled between one or more dies in the stack of dies and the host interface; and

logic in the controller die to program one or more neuromorphic weights into the one or more neuromorphic layers.

14 . The memory system of claim 13 , wherein the one or more neuromorphic layers includes multiple layers in a single die.

15 . The memory system of claim 13 , wherein the one or more neuromorphic layers includes multiple layers in multiple dies.

16 . The memory system of claim 13 , wherein the one or more neuromorphic layers includes from 30 to 100 neuromorphic layers.

17 . The memory system of claim 13 , wherein the memory channel within the multiple memory channels is dedicated to two sub-channels of the die stack interface.

18 . The memory system of claim 13 , wherein the memory channel within the multiple memory channels is dedicated to four sub-channels of the die stack interface.

19 . The memory system of claim 13 , wherein each sub-channel is mapped to multiple dies in the stack of memory dies.

20 . The memory system of claim 13 , wherein each sub-channel is mapped to a single die in the stack of memory dies.

Continuity (3)

References Cited (201)