3D stacked memory and vertical interconnect structures for 3D stacked memory
Provided is a 3D stacked memory device having a cell region in which memory stacks are arranged on a substrate. Vertical memory stacks and a vertical interconnect structure are provided in the cell region. The vertical interconnect structure includes: a via-hole formed along a vertical direction of the cell region; and a conductive pillar shaped by filling the via-hole with a conductive material. The vertical interconnect structure is configured to interconnect a top electrode of the vertical memory stack and a conductive region of the substrate along the vertical direction. The 3D stacked memory device has a vertical interconnect structure configured with a vertical wiring plug of a conductive material in a cell region, so that it is possible to facilitate the manufacturing process and providing a vertical interconnect between top and bottom electrodes of the stacked memory device or a peripheral circuit of the substrate.
1. A 3D stacked memory device having a cell region in which memory stacks are arranged on a substrate,
wherein vertical memory stacks and a vertical interconnect structure are provided in the cell region,
wherein the vertical interconnect structure includes:
a via-hole formed along a vertical direction of the cell region;
a conductive pillar shaped by filling the via-hole with a conductive material; and
a gate insulating film stack, a semiconductor layer for forming a channel, and an insulating film which are sequentially arranged between an inner peripheral surface of the via-hole and the conductive pillar,
wherein the insulating film is configured to surround an outer peripheral surface of the conductive pillar, and
wherein a lower end of the vertical interconnect structure is electrically connected to a conductive wiring line, a conductive region provided on the substrate, or a specific wiring line region of a circuit portion.
2. The 3D stacked memory device according to claim 1 ,
wherein the cell region includes:
a stacked structure formed by alternately stacking a gate and an insulating film on the substrate; and
a plurality of cell plugs configured to penetrate through the stacked structure in the vertical direction,
wherein each of the cell plugs is sequentially provided with a gate insulating film stack and a semiconductor layer for forming a channel from an inner peripheral surface of the cell plug,
wherein a center of the cell plug is provided with an oxide pillar made of an insulating material, and
wherein the via-hole of the vertical interconnect structure is formed to penetrate through the stacked structure formed on the substrate, and the gate and the insulating film of the stacked structure are alternately stacked and arranged on a side surface of the vertical interconnect structure.
3. The 3D stacked memory device according to claim 2 , wherein the cell region further includes a trench located between the cell plugs and the via-hole and formed to penetrate through the stacked structure along the vertical direction, with an inner portion thereof being filled with an oxide material.
4. The 3D stacked memory device according to claim 1 ,
wherein the substrate is configured as a semiconductor substrate, or is configured as an insulating material substrate, and
wherein each of the vertical memory stacks includes a gate insulating film stack having a stacked structure in which a plurality of layers including a charge storage layer including traps and an insulating film are stacked.
5. The 3D stacked memory device according to claim 1 , wherein the conductive material constituting the conductive pillar is configured with one of an electrically conductive metal, binary and polyalloy, metal nitride, a doped semiconductor, and a silicide.
6. The 3D stacked memory device according to claim 1 , wherein each of the vertical memory stacks includes a bit cost scalable (BiCS) structure, a pied-shaped BiCS (P-BiCS) structure, a terabit cell array transistor (TCAT) structure, or a stacked memory device array transistor (SMArT) structure.
7. The 3D stacked memory device according to claim 1 ,
wherein the cell region includes:
a stacked structure formed by alternately stacking a gate and a first insulating film on the substrate; and
a plurality of cell plugs formed to penetrate through the stacked structure in the vertical direction,
wherein each of the cell plugs is sequentially provided with a gate insulating film stack, a semiconductor layer for forming a channel, and a second insulating film from an inner peripheral surface of the cell plug,
wherein a center of the cell plug is further provided with a cell conductive electrode formed in a pillar shape filled with a conductive material, and
wherein the via-hole of the vertical interconnect structure is formed to penetrate through the stacked structure formed on the substrate, and the gate and the first insulating film are alternately stacked and arranged on a side surface of the vertical interconnect structure.
8. The 3D stacked memory device according to claim 7 , wherein the cell region further includes a trench arranged between the cell plugs and the via-hole and formed to penetrate through the stacked structure along the vertical direction, with an inner portion thereof being filled with an oxide.
9. The 3D stacked memory device according to claim 1 ,
wherein the cell region includes:
a stacked structure formed by alternately stacking a gate and a first insulating film on the substrate;
an interlayer insulating film arranged under the substrate;
an etching stopper layer arranged in the interlayer insulating film; and
a plurality of cell plugs formed to penetrate through the stacked structure down to the etching stopper layer in the vertical direction,
wherein each of the cell plugs is sequentially provided with a gate insulating film stack, a semiconductor layer for forming a channel, and an insulating film from an inner peripheral surface of the cell plug,
wherein a center of the cell plug is further provided with a cell conductive electrode formed in a pillar shape filled with a conductive material, and
wherein the via-hole of the vertical interconnect structure is formed to penetrate through the stacked structure formed on the substrate, and a gate and a first insulating film are alternately stacked and arranged on a side surface of the vertical interconnect structure.
10. The 3D stacked memory device according to claim 9 ,
wherein the cell region further includes a trench arranged between the cell plugs and the via-hole and formed to penetrate through the stacked structure along the vertical direction, with an inner portion thereof being filled with an oxide material.
11. A 3D stacked memory device having a cell region in which memory stacks are arranged on a substrate,
wherein vertical memory stacks, a trench and a vertical interconnect structure are provided in the cell region,
wherein the vertical interconnect structure includes:
a via-hole formed along a vertical direction of the cell region; and
a conductive pillar shaped by filling the via-hole with a conductive material,
wherein the cell region includes:
a stacked structure formed by alternately stacking an electrode layer and a
control gate with a surface thereof surrounded by a first gate insulating film stack on the substrate and arranged on a side surface of the vertical interconnect structure; and
a plurality of cell plugs formed to penetrate through the stacked structure in the vertical direction,
wherein each of the cell plugs includes a main gate formed in a pillar shape along the vertical direction of the substrate, a second gate insulating film stack along an outer peripheral surface of the main gate, and a channel region formed along an outer peripheral surface of the second gate insulating film stack,
wherein the via-hole of the vertical interconnect structure is formed to penetrate through the stacked structure configured on the substrate,
wherein the trench is arranged between the cell plugs and the via-hole and formed to penetrate through the stacked structure along the vertical direction, with an inner portion thereof being filled with an oxide material and
wherein a lower end of the vertical interconnect structure is electrically connected to a conductive wiring line, a conductive region provided on the substrate, or a specific wiring line region of a circuit portion.
12. The 3D stacked memory device according to claim 11 ,
wherein the vertical interconnect structure is further sequentially provided with a channel and a gate insulating film stack from an inner peripheral surface of the via-hole, and
wherein the gate insulating film stack inside the via-hole is configured to surround an outer peripheral surface of the conductive pillar, and the conductive pillar of the via-hole is configured with a vertical wiring plug.
13. A 3D stacked memory device having a cell region in which memory stacks are arranged on a substrate,
wherein vertical memory stacks, a trench and a vertical interconnect structure are provided in the cell region,
wherein the vertical interconnect structure includes:
a via-hole formed along a vertical direction of the cell region; and
a conductive pillar shaped by filling the via-hole with a conductive material,
wherein the cell region includes:
a stacked structure formed by alternately stacking an electrode layer and a control gate with a surface thereof surrounded by the gate insulating film stack on the substrate; and
a plurality of cell plugs formed to penetrate through the stacked structure in the vertical direction,
wherein each of the cell plugs includes a word line formed in a pillar shape along the vertical direction of the substrate, a gate insulating film stack formed on an outer peripheral surface of the word line, and a semiconductor layer for forming a channel in a pipe shape formed between the electrode layers along an outer peripheral surface of the gate insulating film stack,
wherein the trench is arranged between the cell plugs and the via-hole and formed to penetrate through the stacked structure along the vertical direction, with an inner portion thereof being filled with an oxide, and
wherein a lower end of the vertical interconnect structure is electrically connected to a conductive wiring line, a conductive region provided on the substrate, or a specific wiring line region of a circuit portion.
14. The 3D stacked memory device according to claim 13 ,
wherein the via-hole of the vertical interconnect structure is formed to penetrate through the stacked structure configured on the substrate, and an insulating layer and an electrode layer are alternately stacked and arranged on a side surface of the vertical interconnect structure with a semiconductor layer for forming a channel in a pipe shape between the electrode layers along an outer peripheral surface of the via-hole,
wherein the vertical interconnect structure further includes a gate insulating film stack along an inner peripheral surface of the via-hole, and
wherein the gate insulating film stack is configured to surround an outer peripheral surface of the conductive pillar, and the conductive pillar of the via-hole is configured with a vertical wiring plug.
15. The 3D stacked memory device according to claim 13 , wherein the via-hole of the vertical interconnect structure is formed to penetrate through one of the electrode layers of the stacked structure configured on the substrate in the vertical direction, and the conductive pillar of the via-hole is configured with a vertical wiring plug.