IP Library Granted Patent US 10,628,295
Granted Patent B2
US 10,628,295 · App. 15/913,758 · Granted Apr 21, 2020

Computing mechanisms using lookup tables stored on memory

Inventors: Peng Gu (Santa Barbara, CA); Krishna T. Malladi (San Jose, CA); Hongzhong Zheng (Los Gatos, CA)
Assignee: Samsung Electronics Co., Ltd.
G06F12/0207G06F7/00G06F7/4876G06F9/3001G06F17/16G06F2212/1024
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Quick Facts
Patent No.
US 10,628,295
App. No.
15/913,758
Granted
Apr 21, 2020
Kind
B2
Abstract

According to some example embodiments of the present disclosure, in a method for a memory lookup mechanism in a high-bandwidth memory system, the method includes: using a memory die to conduct a multiplication operation using a lookup table (LUT) methodology by accessing a LUT, which includes floating point operation results, stored on the memory die; sending, by the memory die, a result of the multiplication operation to a logic die including a processor and a buffer; and conducting, by the logic die, a matrix multiplication operation using computation units.

Claims (79)

1. A method for a memory lookup mechanism in a memory system, the method comprising:

performing, by a memory die, a multiplication operation using a lookup table (LUT) methodology by accessing a LUT, which comprises floating point operation results, stored on the memory die;

sending, by the memory die, a result of the multiplication operation to a logic die comprising a processor and a buffer; and

performing, by the logic die, a matrix multiplication operation using the result of the multiplication operation performed on the memory die.

2. The method of claim 1 , wherein the LUT methodology comprises a floating point full product multiplication method comprising:

retrieving, by the memory die, a whole scalar multiplication result from the LUT using a whole scalar floating point input, the LUT comprising whole product multiplication results;

sending, by the memory die, the whole scalar multiplication result of from the LUT to the buffer;

sending, by the buffer, the whole scalar multiplication result to an accumulator on the logic die; and

accumulating, by the accumulator, the whole scalar multiplication result.

3. The method of claim 1 , wherein the LUT methodology comprises a floating point partial product multiplication method comprising:

using, by the memory die, a fraction scalar floating point input to retrieve a partial product multiplication result from the LUT, which comprises partial product multiplication results;

sending, by the memory die, the partial product multiplication result to the buffer;

sending, by the buffer, the partial product multiplication result to an adjustor on the logic die;

sending, by the adjustor, the partial product multiplication result to an accumulator on the logic die; and

accumulating, by the accumulator, the partial product multiplication result.

4. The method of claim 1 , wherein the LUT methodology comprises a floating point tensor operation method, the floating point tensor operation method comprising:

retrieving, by the memory die, a tensor multiplication result from the LUT using a tensor floating point input, the LUT comprising tensor multiplication results;

sending, by the memory die, the tensor multiplication result to the buffer; and

sending, by the buffer, the tensor multiplication result to a tensor post-processor on the logic die.

5. The method of claim 1 , wherein the LUT methodology comprises a floating point fused layer operation method, the method comprising:

retrieving, by the memory die, a whole scalar multiplication result from the LUT using a whole scalar floating point, wherein the LUT comprises whole product multiplication results;

sending, by the memory die, the whole product multiplication results to a buffer die comprising a plurality of buffers separate from the buffer of the logic die;

sending, by the buffer die, the whole product multiplication result to the buffer of the logic die; and

sending, by the buffer of the logic die, the whole product multiplication result to a tensor processor on the logic die.

6. The method of claim 1 , further comprising:

storing the LUT associated with a first type of operation on the memory die; and

storing the LUT associated with a second type of operation that is different from the first type of operation on the memory die.

7. The method of claim 1 , further comprising:

reading every possible location in a first layer input feature map;

convolving with the first layer input feature map with a first layer kernel; and

generating results of a second layer input feature map based on the convolving.

8. A memory lookup mechanism comprising: a logic die comprising a processor and a buffer, wherein the processor performs a matrix multiplication operation using computational units; and a memory die comprising a lookup table (LUT),

wherein the LUT comprises floating point operation results, and

wherein the memory die performs operations comprising: accessing the LUT;

performing a multiplication operation using a LUT methodology; and

sending a result of the multiplication operation to the logic die for use by the logic die to perform matrix multiplication operations.

9. The memory lookup mechanism of claim 8 , wherein the memory die performs operations further comprising:

retrieving a whole scalar multiplication result from the LUT using a whole scalar floating point input, wherein the LUT comprises whole product multiplication results; and

sending the whole scalar multiplication result from the LUT to the buffer.

10. The memory lookup mechanism of claim 9 , wherein the logic die further comprises an accumulator, the accumulator performing operations comprising:

receiving the whole scalar multiplication result from the buffer; and

accumulating the whole scalar multiplication result.

11. The memory lookup mechanism of claim 8 , wherein the memory die performs operations further comprising:

retrieving a partial product multiplication result from the LUT using a fraction scalar floating point input, wherein the LUT comprises partial product multiplication results; and

sending the partial product multiplication result to the buffer.

12. The memory lookup mechanism of claim 11 , wherein the logic die further comprises:

an adjustor, the adjustor receiving the partial product multiplication result from the buffer; and

an accumulator, the accumulator performing operations comprising:

receiving the partial product multiplication result from the adjustor; and

accumulating the partial product multiplication result.

13. The memory lookup mechanism of claim 8 , wherein the memory die performs operations further comprising:

retrieving a tensor multiplication result from the LUT comprising tensor multiplication results using a tensor floating point input; and

sending the tensor multiplication result to the buffer.

14. The memory lookup mechanism of claim 13 , wherein the logic die further comprises a tensor post-processor receiving the tensor multiplication result from the buffer.

15. The memory lookup mechanism of claim 8 , wherein the memory die performs operations further comprising:

retrieving a whole scalar multiplication result from the LUT using a whole scalar floating point, wherein the LUT comprises whole product multiplication results; and

sending the whole product multiplication results to a buffer die.

16. The memory lookup mechanism of claim 15 , wherein the logic die further comprises a tensor processor, the processor receiving the whole product multiplication results from the buffer die.

17. The memory lookup mechanism of claim 8 , wherein the logic die further comprises an accelerator die.

18. The memory lookup mechanism of claim 8 , wherein the memory die comprises a dynamic random access memory (DRAM) die.

19. A memory die comprising a lookup table (LUT) stored thereon, and configured to perform:

a floating point full product multiplication method comprising:

retrieving, by the memory die, a whole scalar multiplication result from the LUT using a whole scalar floating point input, the LUT comprising whole product multiplication results;

sending, by a buffer, the whole scalar multiplication result to an accumulator; and

accumulating, by the accumulator, the whole scalar multiplication result;

a floating point partial product multiplication method comprising:

retrieving, by the memory die, a partial product multiplication result from the LUT using a fraction scalar floating point input, the LUT comprising partial product multiplication results;

sending, by the memory die, the partial product multiplication result to the buffer;

sending, by the buffer, the partial product multiplication result to an adjustor;

accumulating, by the accumulator, the partial product multiplication result;

a floating point tensor operation method comprising:

retrieving, by the memory die, a tensor multiplication result from the LUT using a tensor floating point input, the LUT comprising tensor multiplication results;

sending, by the memory die, the tensor multiplication result to the buffer;

sending, by the buffer, the tensor multiplication result to a tensor post-processor; and

a floating point fused layer operation method comprising:

retrieving, by the memory die, a whole scalar multiplication result from the LUT using, a whole scalar floating point wherein the LUT comprises whole product multiplication results;

sending, by the memory die, the whole product multiplication results to a buffer die comprising a plurality of buffers;

sending, by the buffer die, the whole product multiplication result to the buffer; and

sending, by the buffer, the whole product multiplication result to a tensor processor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 24, 2018
From: GU, PENG; MALLADI, KRISHNA T.; ZHENG, HONGZHONG
To: SAMSUNG ELECTRONICS CO., LTD
Reel/Frame 045899/0047 →
Continuity (2)
Provisional Application 62610439 · Dec 26, 2017
Related Publication 20190196953A1 · Jun 27, 2019
Cited By (5)
US 12,217,092 US 12,253,943 US 12,277,056 US 12,300,349 US 12,639,236