On-die termination control without a dedicated pin in a multi-rank system
A memory subsystem includes a multi-device package including multiple memory devices organized as multiple ranks of memory. A control unit for the memory subsystem sends a memory access command concurrently to some or all of the ranks of memory, and triggers some of all of the memory ranks that receive the memory access command to change on-die termination (ODT) settings. One of the ranks is selected to execute the memory access command, and executes the command while all ranks triggered to change the ODT setting have the changed ODT setting.
1. A memory controller to control on-die termination, comprising:
logic to identify, for a multi-rank system, a target dynamic random access memory (DRAM) device and a non-target DRAM device; and
input/output interface hardware to
send a command to set a setting of a register of the non-target DRAM device to indicate a non-target termination impedance for on-die termination (ODT), and
send a memory access command to the target DRAM device and the non-target DRAM device, followed by a CAS-2 (column address selection) command to the target DRAM device and a non-target CAS-2 command to the non-target DRAM device;
wherein the non-target DRAM device is to apply the non-target termination impedance to a data signal line in response to receipt of the non-target CAS-2 command.
2. The memory controller of claim 1 , wherein the memory access command comprises a Read command.
3. The memory controller of claim 2 , wherein the memory access command comprises a Read-1 command.
4. The memory controller of claim 1 , wherein the memory access command comprises a Write command.
5. The memory controller of claim 4 , wherein the memory access command comprises a Write-1 command.
6. The memory controller of claim 1 , wherein the memory access command comprises a two-cycle command and the non-target CAS-2 command comprises a two-cycle command.
7. The memory controller of claim 6 , wherein the input/output interface hardware is to assert a chip select (CS) signal on a first cycle of the memory access command, and wherein the input/output interface hardware is to not assert a CS signal on a first cycle of the non-target CAS-2 command.
8. The memory controller of claim 1 , wherein the command to set the setting of the register comprises a mode register set (MRS) command to set a mode register of the non-target DRAM device.
9. The memory controller of claim 8 , wherein the input/output interface hardware is to send the MRS command after the non-target CAS-2 command to change a termination impedance setting for a subsequent memory access.
10. The memory controller of claim 1 , wherein the target DRAM device and non-target DRAM device comprise devices compatible with a double data rate version 4 (LPDDR4) standard.
11. The memory controller of claim 1 , wherein the non-target DRAM device is to apply ODT in accordance with the termination resistance for non-target termination without an ODT control pin.
12. The memory controller of claim 1 , wherein the memory controller is integrated on a common substrate with a processor.
13. A system for providing termination on a memory access, comprising:
multiple memory ranks, wherein a memory rank includes one or more dynamic random access memory (DRAM) devices; and
a memory controller coupled to the multiple memory ranks, the memory controller including:
input/output interface hardware to
send a command to set a setting of a register of the non-target DRAM device to indicate a non-target termination impedance for on-die termination (ODT), and
send a memory access command to the target DRAM device and the non-target DRAM device, followed by a CAS-2 (column address selection) command to the target DRAM device and a non-target CAS-2 command to the non-target DRAM device;
wherein the non-target DRAM device is to apply the non-target termination impedance to a data signal line in response to receipt of the non-target CAS-2 command.
14. The system of claim 13 , wherein the memory access command comprises a Read-1 command or a Write-1 command.
15. The system of claim 13 , wherein the memory access command comprises a two-cycle command and the non-target CAS-2 command comprises a two-cycle command, wherein the input/output interface hardware is to assert a chip select (CS) signal on a first cycle of the memory access command, and wherein the input/output interface hardware is to not assert a CS signal on a first cycle of the non-target CAS-2 command.
16. The system of claim 13 , wherein the command to set the setting of the register comprises a mode register set (MRS) command to set a mode register of the non-target DRAM device.
17. The system of claim 16 , wherein the input/output interface hardware is to send the MRS command after the non-target CAS-2 command to change a termination impedance setting for a subsequent memory access.
18. The system of claim 11 , wherein the target DRAM device and the non-target DRAM device comprise devices compatible with a double data rate version 4 (LPDDR4) standard.
19. The system of claim 11 , wherein the memory controller comprises a circuit integrated onto a common substrate with a multicore processor.
20. The system of claim 11 , further comprising one or more of:
at least one processor communicatively coupled to the memory controller;
a display communicatively coupled to at least one processor;
a battery to power the system; or
a network interface communicatively coupled to at least one processor.
21. A method for providing termination on a memory access, comprising:
identifying for multiple connected dynamic random access memory (DRAM) devices, at least one target DRAM device and at least one non-target DRAM device;
sending a memory access command followed by a CAS-2 (column address selection) command to the target DRAM device; and
sending the memory access command followed by a non-target CAS-2 command to the non-target DRAM device to cause the non-target DRAM device to apply a non-target termination impedance with on-die termination (ODT) to a data signal line.
22. The method of claim 21 , wherein the memory access command comprises a Read-1 command or a Write-1 command.
23. The method of claim 21 , wherein the memory access command comprises a two-cycle command and the non-target CAS-2 command comprises a two-cycle command, wherein the input/output interface hardware is to assert a chip select (CS) signal on a first cycle of the memory access command, and wherein the input/output interface hardware is to not assert a CS signal on a first cycle of the non-target CAS-2 command.
24. The method of claim 21 , further comprising:
sending a mode register set (MRS) command to set an ODT setting of the DRAM devices.