Artificial neuron apparatus

1. An artificial neuron apparatus, comprising:

a first resistive memory cell connected in first circuitry having a first neuron input, for receiving excitatory neuron input signals, and a first output;

a second resistive memory cell connected in second circuitry having a second neuron input, for receiving inhibitory neuron input signals, and a second output;

said first and second circuitry being operable in alternating read and write phases to apply a programming current, for programming cell resistance, to their respective memory cells on receipt of an excitatory and an inhibitory neuron input signal respectively during said write phase, whereby resistance of the respective cells is progressively changed in response to successive excitatory and inhibitory neuron input signals respectively, and, during said read phase, to apply a read current to their respective cells to produce first and second measurement signals respectively, dependent on resistance of the respective cells, at the first and second outputs respectively; and

an output circuit connected to said first and second outputs and configured to produce a neuron output signal at a neuron output if a difference between said first and second measurement signals traverses a threshold;

wherein the output circuit comprises a threshold difference circuit connected to said first and second outputs and operable to output a difference signal dependent on said difference, wherein the difference signal corresponds to a first digital value if said difference traverses said threshold, and a second digital value otherwise;

wherein the threshold difference circuit comprises a current mirror and a trigger-adjustable inverter, the current mirror being connected to said first and second outputs and operable to provide a difference output, dependent on said difference, to the trigger-adjustable inverter, and the trigger-adjustable inverter being operable in response to said difference output to produce the difference signal corresponding to one of said first and second digital values;

wherein the output circuit comprises:

a digital latch operable in said read phase to latch a digital value dependent on said difference signal; and

a logic gate connected between the latch and said neuron output and operable in said write phase, in response to the latched digital value, to provide said neuron output signal at the neuron output if said difference traverses said threshold.

2. The apparatus as claimed in claim 1 , wherein each of the first and second circuitry is selectively configurable for operation in said read and write phases in response to a set of control signals defining the read and write phases.

3. The apparatus as claimed in claim 2 , wherein the first and second circuitry are further configurable in response to said neuron output signal to apply a reset current to their respective memory cells for resetting the cells to an initial resistance state.

4. The apparatus as claimed in claim 3 , wherein the first and second circuitry are further configurable in response to a neuron reset signal, received during said write phase, to apply a reset current to their respective memory cells for resetting the cells to said initial resistance state.

5. The apparatus as claimed in claim 4 , wherein:

each of the first and second circuitry comprises a current source for supplying said read current to the respective memory cell during said read phase; and

the first circuitry comprises a plurality of access devices connected between a first terminal of the first memory cell and a reference terminal of the circuitry, respective access devices enabling current flow through the first cell in response to said read phase, said excitatory neuron input signals, said neuron output signal, and said neuron reset signal; and

the second circuitry comprises a plurality of access devices connected between a first terminal of the second memory cell and a reference terminal of the circuitry, respective access devices enabling current flow through the second cell in response to said read phase, said inhibitory neuron input signals, said neuron output signal, and said neuron reset signal.

6. The apparatus as claimed in claim 2 , wherein:

each of the first and second circuitry comprises a current source for supplying said read current to the respective memory cell during said read phase; and

the first circuitry comprises at least one access device, connected between a first terminal of the first memory cell and a reference terminal of the circuitry, for enabling current flow through the first cell in response to said read phase and said excitatory neuron input signals; and

the second circuitry comprises at least one access device, connected between a first terminal of the second memory cell and a reference terminal of the circuitry, for enabling current flow through the second cell in response to said read phase and said inhibitory neuron input signals.

7. The apparatus as claimed in claim 6 , wherein:

said current source in each of said first and second circuitry is connected to a second terminal of the respective memory cell;

each of the first and second circuitry includes a switch connected to said second terminal, the switch being configured to apply said programming current to the cell during said write phase; and

each of the first and second outputs is connected to said second terminal of the respective memory cell.

8. The apparatus as claimed in claim 7 , wherein the digital latch is configured to latch said digital value output by the threshold difference circuit, and said logic gate comprises a NOR gate.

9. The apparatus as claimed in claim 7 , wherein the output circuit comprises an inverter connected between the threshold difference circuit and the digital latch, and wherein said logic gate comprises an AND gate.