Memory module with memory stack and interface with enhanced capabilities
A memory module, which includes at least one memory stack, comprises a plurality of DRAM integrated circuits and an interface circuit. The interface circuit interfaces the memory stack to a host system so as to operate the memory stack as a single DRAM integrated circuit. In other embodiments, a memory module includes at least one memory stack and a buffer integrated circuit. The buffer integrated circuit, coupled to a host system, interfaces the memory stack to the host system so to operate the memory stack as at least two DRAM integrated circuits. In yet other embodiments, an interface circuit maps virtual addresses from the host system to physical addresses of the DRAM integrated circuits in a linear manner. In a further embodiment, the interface circuit maps one or more banks of virtual addresses from the host system to a single one of the DRAM integrated circuits. In yet other embodiments, the buffer circuit interfaces the memory stack to the host system for transforming one or more physical parameters between the DRAM integrated circuits and the host system. In still other embodiments, the buffer circuit interfaces the memory stack to the host system for configuring one or more of the DRAM integrated circuits in the memory stack. Neither the patentee nor the USPTO intends for details set forth in the abstract to constitute limitations to claims not explicitly reciting those details.
1. A memory module comprising:
at least one memory stack that comprises a plurality of dynamic random access memory (DRAM) integrated circuits; and
a buffer circuit, configured to be coupled to a host system, for interfacing said at least one memory stack to said host system for configuring one or more of said DRAM integrated circuits in said memory stack;
wherein said at least one memory stack comprises at least one non-volatile memory device, and
wherein said buffer circuit is further configured for copying data from at least one of said DRAM integrated circuits to said at least one non-volatile memory device upon detection of a catastrophic event.
2. The memory module as set forth in claim 1 , wherein:
said DRAM integrated circuits comprise slow DRAM integrated circuits; and
said buffer circuit is further configured for emulating high-speed DRAM operation to said host system.
3. The memory module as set forth in claim 1 , wherein:
said buffer circuit is further configured for exposing a greater number of banks than a number of banks in said memory stack.
4. The memory module as set forth in claim 1 , wherein:
said buffer circuit is further configured for exposing a lesser number of banks than a number of banks in said memory stack.
5. The memory module as set forth in claim 1 , wherein the catastrophic event comprises a system crash.
6. The memory module as set forth in claim 1 , wherein the catastrophic event comprises a power supply failure.
7. The memory module as set forth in claim 1 , wherein the DRAM integrated circuits comprise DDR SDRAMS or DDR2 SDRAMS.
8. The memory module as set forth in claim 1 , wherein the buffer circuit is included in the at least one memory stack with the DRAM integrated circuits.
9. The memory module as set forth in claim 1 , wherein the buffer circuit is included in a separate stack from the at least one memory stack that includes the DRAM integrated circuits.
10. The memory module as set forth in claim 1 , wherein the at least one memory stack comprises at least two memory stacks with a first stack being on a first side of a PCB and controlled by the buffer circuit and a second stack being on a second side of the PCB and controlled by a second buffer circuit.
11. The memory module as set forth in claim 1 , wherein the at least one non-volatile memory device comprises at least one flash device.
12. The memory module as set forth in claim 1 , wherein the buffer circuit is configured to detect the catastrophic event.
13. The memory module as set forth in claim 1 , wherein the buffer circuit is further configured to periodically copy data from at least one of said DRAM integrated circuits to said at least one non-volatile memory device upon receipt of a command from the host system.
14. The memory module as set forth in claim 1 , wherein the module further comprises a back-up power source configured to provide back-up power to the buffer circuit and the DRAM integrated circuits upon detection of the catastrophic event.
15. The memory module as set forth in claim 14 , wherein the module further comprises an isolation switch.
16. The memory module as set forth in claim 14 , wherein the back-up power source comprises a battery.
17. The memory module as set forth in claim 14 , wherein the back-up power source comprises a capacitor.
18. The memory module as set forth in claim 1 , wherein the buffer circuit is further configured to generate signals to preserve contents of the DRAM integrated circuits upon detection of the catastrophic event.
19. The memory module as set forth in claim 1 , wherein the buffer circuit is further configured to generate refresh signals for the DRAM integrated circuits upon detection of the catastrophic event.
20. The memory module as set forth in claim 1 , wherein the buffer circuit is further configured to decouple a memory bus of the host system from the at least one memory stack upon detection of the catastrophic event.