Memory module and memory system including the memory module
A memory system may include a controller; and a plurality of memory modules, wherein a data input and output of the plurality of memory modules is performed with a single channel manner according to an address signal provided from the controller in common, wherein each of the plurality of memory modules includes a buffer chip and a plurality of memory chips coupled to the buffer chip, wherein all the buffer chips of the plurality of memory modules are directly coupled to the controller through independent input and output bus.
1. A memory system comprising:
a controller; and
a plurality of memory modules,
wherein a data input and output of the plurality of memory modules is performed with a single channel manner according to an address signal provided from the controller in common,
wherein each of the plurality of memory modules includes a buffer chip and a plurality of memory chips in a row direction coupled to the buffer chip,
wherein memory chips in a column direction consisting of selected one by one in each memory module of the plurality of the memory modules constitutes a rank, and
wherein all the buffer chips of the plurality of memory modules are directly coupled to the controller through independent input and output bus.
2. The memory system of claim 1 , wherein data I/O is performed by selecting one or more memory chips from each of the plurality of memory modules according to a select signal provided from the controller.
3. The memory system of claim 1 ,
wherein data I/O is performed by selecting one or more memory chips from each of the plurality of memory modules according to a select signal provided from the controller, and
wherein the one or more memory chips selected from the plurality of memory modules are arranged on the same line.
4. The memory system of claim 1 ,
wherein the plurality of memory chips are distributed and arranged on left and right sides of the buffer chip, and
wherein an equal number of memory chips are located on the right side and the left side of the buffer chip.
5. The memory system of claim 1 ,
wherein the buffer chip includes:
a controller configured to generate control signals for controlling a data I/O operation between the plurality memory chips and the controller according to an address signal and a select signal;
a read multiplexing circuit configured to selectively output data output from the plurality of memory chips according to the control signals; and
a write multiplexing circuit configured to selectively transfer data input from the controller to the plurality of memory chips according to the control signals.
6. The memory system of claim 5 ,
wherein the read multiplexing circuit includes:
a plurality of latches configured to generate latch signals by latching the data output from the plurality of memory chips according to strobe signals and the control signals; and
a multiplexer configured to selectively output the latch signals according to the control signals.
7. The memory system of claim 5 ,
wherein the write multiplexing circuit includes:
a multiplexer configured to selectively output the data input from the controller according to the control signals; and
a plurality of variable delays configured to receive an output signal of the multiplexer according to the control signals and output delayed signals by delaying the received output signal by a preset time, and
wherein delay times of the plurality of variable delays are set according to distances between the buffer chip and the plurality of memory chips.
8. The memory system of claim 1 ,
wherein the buffer chip includes:
a controller configured to generate control signals for controlling a data I/O operation between the plurality of memory chips and the controller according to an address signal and a select signal;
a serializing and parallelizing (serializing/parallelizing) circuit configured to output data output from different two memory chips among the plurality of memory chips through serialization or output data input from the controller to the different two memory chips through parallelization;
a read multiplexing circuit configured to selectively output data output from the serializing/parallelizing circuit according to the control signals; and
a write multiplexing circuit configured to transfer the data input from the controller to the serializing/parallelizing circuit according to the control signals.
9. The memory system of claim 1 , wherein the number of I/O lines in each of the plurality of memory modules is smaller than that of the controller.
10. A memory system comprising:
a controller; and
a plurality of memory modules,
wherein a data input and output of the plurality of memory modules is performed with a single channel manner according to an address signal provided from the controller in common,
wherein each of the plurality of memory modules includes a buffer chip and a plurality of memory chips in a row direction coupled to the buffer chip,
wherein memory chips in a column direction consisting of selected one by one in each memory module of the plurality of the memory modules constitutes a rank,
wherein all the buffer chips of the plurality of memory modules are directly coupled to the controller through independent input and output bus.
11. The memory system of claim 10 ,
wherein the plurality of memory chips are distributed and arranged on left and right sides of the buffer chip, and
wherein an equal number of memory chips are located on the right side and the left side of the buffer chip.
12. The memory system of claim 10 ,
wherein the buffer chip includes:
a controller configured to generate control signals for controlling a data I/O operation between the plurality memory chips and the controller according to an address signal and a select signal;
a read multiplexing circuit configured to selectively output data output from the plurality of memory chips according to the control signals; and
a write multiplexing circuit configured to selectively transfer data input from the controller to the plurality of memory chips according to the control signals.
13. The memory system of claim 12 ,
wherein the read multiplexing circuit includes:
a plurality of latches configured to generate latch signals by latching the data output from the plurality of memory chips according to strobe signals and the control signals; and
a multiplexer configured to selectively output the latch signals according to the control signals.
14. The memory system of claim 12 ,
wherein the write multiplexing circuit includes:
a multiplexer configured to selectively output the data input from the controller according to the control signals; and
a plurality of variable delays configured to receive an output signal of the multiplexer according to the control signals and output delayed signals by delaying the received output signal by a preset time, and
wherein delay times of the plurality of variable delays are set according to distances between the buffer chip and the plurality of memory chips.
15. The memory system of claim 10 ,
wherein the buffer chip includes:
a controller configured to generate control signals for controlling a data I/O operation between the plurality of memory chips and the controller according to an address signal and a select signal;
a serializing and parallelizing (serializing/parallelizing) circuit configured to output data output from different two memory chips among the plurality of memory chips through serialization or output the data input from the controller to the different two memory chips through parallelization;
a read multiplexing circuit configured to selectively output data output from the serializing/parallelizing circuit according to the control signals; and
a write multiplexing circuit configured to transfer the data input from the controller to the serializing/parallelizing circuit according to the control signals.
16. The memory system of claim 10 , wherein the number of I/O lines in each of the plurality of memory modules is smaller than that of the controller.