Gate-all-around integrated circuit structures having germanium-diffused nanoribbon channel structures
Gate-all-around integrated circuit structures having germanium-diffused nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having germanium-diffused nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a sub-fin structure, wherein individual ones of the vertical arrangement of nanowires include silicon and germanium, and wherein the sub-fin structure has a relatively higher germanium concentration at a top of the sub-fin structure than at a bottom of the sub-fin structure.
1. An integrated circuit structure, comprising:
a vertical arrangement of nanowires above a sub-fin structure, wherein individual ones of the vertical arrangement of nanowires comprise silicon and germanium, and wherein the sub-fin structure has a relatively higher germanium concentration at a top of the sub-fin structure than at a bottom of the sub-fin structure;
an isolation structure laterally adjacent to the sub-fin structure, the isolation structure having a top surface below the top of the sub-fin structure; and
a gate stack over the vertical arrangement of nanowires, the gate stack intervening between individual ones of the vertical arrangement of nanowires, the gate stack having a bottommost surface below the top of the sub-fin structure, and the gate stack laterally adjacent to a portion of the sub-fin structure having a lower germanium concentration than the top of the sub-fin structure.
2. The integrated circuit structure of claim 1 , wherein the bottom of the sub-fin structure does not include germanium.
3. The integrated circuit structure of claim 1 , further comprising:
epitaxial source or drain structures at the lateral ends of the vertical arrangement of nanowires.
4. The integrated circuit structure of claim 3 , wherein the epitaxial source or drain structures are non-discrete epitaxial source or drain structures.
5. The integrated circuit structure of claim 3 , wherein the epitaxial source or drain structures are discrete epitaxial source or drain structures.
6. The integrated circuit structure of claim 1 , wherein the sub-fin structure extends from a substrate.
7. An integrated circuit structure, comprising:
a first vertical arrangement of nanowires, wherein individual ones of the first vertical arrangement of nanowires comprise silicon;
a second vertical arrangement of nanowires above a sub-fin structure, wherein the sub-fin structure has a relatively higher germanium concentration at a top of the sub-fin structure than at a bottom of the sub-fin structure, wherein individual ones of the second vertical arrangement of nanowires comprise silicon and germanium, and wherein individual ones of the second vertical arrangement of nanowires are in a same plane as a corresponding individual one of the first vertical arrangement of nanowires;
an isolation structure laterally adjacent to the sub-fin structure, the isolation structure having a top surface below the top of the sub-fin structure; and
a gate stack over the second vertical arrangement of nanowires, the gate stack intervening between individual ones of the second vertical arrangement of nanowires, the gate stack having a bottommost surface below the top of the sub-fin structure, and the gate stack laterally adjacent to a portion of the sub-fin structure having a lower germanium concentration than the top of the sub-fin structure.
8. The integrated circuit structure of claim 7 , wherein the first vertical arrangement of nanowires is above a second sub-fin structure comprising silicon.
9. The integrated circuit structure of claim 7 , wherein the bottom of the sub-fin structure does not include germanium.
10. The integrated circuit structure of claim 7 , wherein individual ones of the first vertical arrangement of nanowires consist essentially of silicon.
11. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a vertical arrangement of nanowires above a sub-fin structure, wherein individual ones of the vertical arrangement of nanowires comprise silicon and germanium, and wherein the sub-fin structure has a relatively higher germanium concentration at a top of the sub-fin structure than at a bottom of the sub-fin structure;
an isolation structure laterally adjacent to the sub-fin structure, the isolation structure having a top surface below the top of the sub-fin structure; and
a gate stack over the vertical arrangement of nanowires, the gate stack intervening between individual ones of the vertical arrangement of nanowires, the gate stack having a bottommost surface below the top of the sub-fin structure and the gate stack laterally adjacent to a portion of the sub-fin structure having a lower germanium concentration than the top of the sub-fin structure.
12. The computing device of claim 11 , further comprising:
a memory coupled to the board.
13. The computing device of claim 11 , further comprising:
a communication chip coupled to the board.
14. The computing device of claim 11 , further comprising:
a camera coupled to the board.
15. The computing device of claim 11 , further comprising:
a battery coupled to the board.
16. The computing device of claim 11 , further comprising:
an antenna coupled to the board.
17. The computing device of claim 11 , wherein the component is a packaged integrated circuit die.
18. The computing device of claim 11 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.
19. An integrated circuit structure, comprising:
a first vertical arrangement of nanowires above a substrate, wherein individual ones of the first vertical arrangement of nanowires comprise silicon, wherein the first vertical arrangement of nanowires is above a first sub-fin structure comprising silicon;
a second vertical arrangement of nanowires above the substrate, wherein individual ones of the second vertical arrangement of nanowires comprise silicon and germanium, wherein individual ones of the second vertical arrangement of nanowires are in a same plane as a corresponding individual one of the first vertical arrangement of nanowires, wherein the second vertical arrangement of nanowires is above a second sub-fin structure comprising silicon and germanium, and wherein the second sub-fin structure has a relatively higher germanium concentration at a top of the second sub-fin structure than at a bottom of the second sub-fin structure; and
a gate stack over the second vertical arrangement of nanowires, the gate stack intervening between individual ones of the second vertical arrangement of nanowires, the gate stack having a bottommost surface below the top of the sub-fin structure, and the gate stack laterally adjacent to a portion of the sub-fin structure having a lower germanium concentration than the top of the sub-fin structure.
20. The integrated circuit structure of claim 19 , wherein the bottom of the second sub-fin structure does not include germanium.