IP Library Granted Patent US 11,690,265
Granted Patent B2
US 11,690,265 · App. 17/134,587 · Granted Jun 27, 2023

Display device having a trench portion

Inventors: Kiwook Kim (Yongin-si, KR); Kwangmin Kim (Yongin-si, KR); Jisu Na (Yongin-si, KR); Minwoo Byun (Yongin-si, KR)
Assignee: SAMSUNG DISPLAY CO., LTD.
H10K59/131H10K50/844H10K59/1315H10K77/10H10K50/8426
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Quick Facts
Patent No.
US 11,690,265
App. No.
17/134,587
Granted
Jun 27, 2023
Kind
B2
Abstract

A display device includes a substrate including a trench portion. The substrate includes a display area and a peripheral area adjacent to the display area. The display area includes a first display area and a second display area arranged with the trench portion therebetween to display an image. A thin-film transistor and a display element are each arranged in the display area. A built-in circuit portion is over the peripheral area and is adjacent to the trench portion. A first wiring is in the first display area and a second wiring is in the second display area. A connecting wiring connects the first wiring to the second wiring and overlaps the built-in circuit portion.

Claims (59)

1. A display device comprising:

a substrate including a display area and a non-display area, wherein the display area comprises a first display area and a second display area, and the non-display area at least partially disposed between the first display area and the second display area,

a thin-film transistor and a display element, each arranged in the display area;

a built-in circuit portion over the non-display area, wherein the built-in circuit portion is at least partially disposed between the first display area and the second display area;

a first wiring in the first display area;

a second wiring in the second display area; and

a connecting wiring connecting the first wiring to the second wiring, wherein the connecting wiring is disposed in the non-display area, and

wherein the connecting wiring overlaps the built-in circuit portion over the non-display area and has a bent portion.

2. The display device of claim 1 , wherein the built-in circuit portion comprises a plurality of stages comprising at least one peripheral thin-film transistor, and

the connecting wiring overlaps the at least one peripheral thin-film transistor.

3. The display device of claim 1 , further comprising:

a scan line connected to the built-in circuit portion and overlapping the display area,

wherein the scan line intersects the connecting wiring in a layer different from that of the connecting wiring.

4. The display device of claim 1 , wherein the connecting wiring comprises a first connecting wiring and a second connecting wiring adjacent to each other, and

a shortest distance between the first connecting wiring and the second connecting wiring in a region not overlapping the built-in circuit portion is greater than a shortest distance between the first connecting wiring and the second connecting wiring in a region overlapping the built-in circuit portion.

5. The display device of claim 1 , wherein the connecting wiring comprises a first connecting wiring and a second connecting wiring adjacent to each other, and

the first connecting wiring and the second connecting wiring in a region overlapping the built-in circuit portion are curved.

6. The display device of claim 5 , wherein a degree of curvature of the first connecting wiring and a degree of curvature of the second connecting wiring in the region overlapping the built-in circuit portion are different from each other.

7. The display device of claim 1 , wherein the substrate includes a trench portion recessed from one side of the substrate to the display area in a plan view, the trench portion is disposed between the first display area and the second display area.

8. The display device of claim 1 , further comprising,

an inorganic protective layer substantially covering the first wiring and the second wiring; and

a planarization layer disposed on the inorganic protective layer,

wherein the connecting wiring is located over the planarization layer and connected to the first wiring and the second wiring through a first contact hole and a second contact hole penetrating the planarization layer and the inorganic protective layer, respectively.

9. A display device comprising:

a substrate including a display area and a non-display area, wherein the display area comprises a first display area and a second display area, and the non-display area at least partially disposed between the first display area and the second display area,

a display element arranged in the display area;

a built-in circuit portion over the non-display area, wherein the built-in circuit portion is at least partially disposed between the first display area and the second display area;

a first wiring in the first display area;

a second wiring in the second display area;

a connecting wiring connecting the first wiring to the second wiring, wherein the connecting wiring is disposed in the non-display area;

a first power supply voltage line arranged to correspond to one side of the display area; and

a second power supply voltage line adjacent to at least a portion of the display area,

wherein the built-in circuit portion is located between the display area and the second power supply voltage line.

10. The display device of claim 9 , wherein the second power supply voltage hoe includes a first layer and a second layer on the first layer, the first layer provided in a same layer as that, of the first wiring and the second layer comprising a same material as that of the connecting wiring.

11. The display device of claim 9 , wherein the display element comprises a pixel electrode, an intermediate layer, and an opposite electrode,

a conductive layer is located over the second power supply voltage line, the conductive layer comprising a same material as that of the pixel electrode, and

the opposite electrode overlapping the non-display area and electrically connected to the second power supply voltage line via the conductive layer.

12. The display device of claim 1 , further comprising:

a lower conductive layer overlapping the thin-film transistor with an insulating layer therebetween, the lower conductive layer being located between the substrate and the thin-film transistor,

wherein the connecting wiring is on a same layer as that of the lower conductive layer.

13. The display device of claim 12 , wherein the connecting wiring is connected to the first wiring through a contact hole penetrating the insulating layer.

14. The display device of claim 1 , further comprising:

a thin-film encapsulation layer sealing the display area and comprising at east one inorganic encapsulation layer and at least one organic encapsulation layer; and

a dam portion in the non-display area and protruding from the substrate.

15. The display device of claim 1 , further comprising:

a sealing substrate sealing the display area and facing the substrate; and

a sealing member adjacent to the non-display area and joining the substrate to the sealing substrate.

16. A display device comprising:

a substrate including a display area and a non-display area, wherein the display area comprises a first display area and a second display area, and the non-display area at least partially disposed between the first display area and the second display area,

a thin-film transistor and a display element, each arranged in the display area;

a first built-in circuit portion over the non-display area and adjacent to a first side of the substrate, the first built-in circuit portion comprising at least one peripheral thin-film transistor, wherein the first built-in circuit portion is at least partially disposed between the first display area and the second display area;

a pad portion over a second side intersecting the first side, wherein a controller is mounted on the pad portion;

a first wiring in the first display area and a second wiring in the second display area; and

a connecting wiring connecting the first wiring to the second wiring and overlapping the first built-in circuit portion over the non-display area, wherein the connecting wiring is disposed in the non-display area.

17. The display device of claim 16 , wherein the second side is longer than the first side.

18. The display device of claim 16 , further comprising:

a second built-in circuit portion adjacent to a third side at a side opposite to that of the first side of the substrate.

19. The display device of claim 16 , wherein the connecting wiring overlaps the at least one peripheral thin-film transistor.

20. The display device of claim 16 , wherein at least a portion of the connecting wiring is curved shape.

Priority Claims (1)
KR 10-2018-0083128 · Jul 17, 2018 · national
Continuity (2)
Continuation 16364732 · Mar 26, 2019
Related Publication 20210118974A1 · Apr 22, 2021
Cited By (1)
US 12,633,258