IP Library Granted Patent US 11,363,227
Granted Patent B1
US 11,363,227 · App. 17/134,761 · Granted Jun 14, 2022

Image sensors with hybrid analog-to-digital converter architecture

Inventor: Brian Young (Albany, OR)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H04N5/378H04N5/37455
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Quick Facts
Patent No.
US 11,363,227
App. No.
17/134,761
Granted
Jun 14, 2022
Kind
B1
Abstract

An image sensor may include an image sensor pixel array, row control circuitry, and column readout circuitry. The column readout circuitry may include analog-to-digital converter (ADC) circuitry. The ADC circuitry may have a first portion that selectively converts pixel signals associated with a low light or high conversion gain operating environment and a second portion that converts any pixel signals. As an example, the first portion may be a ramp ADC and the second portion may be a successive approximation register (SAR) ADC.

Claims (36)

1. An image sensor comprising:

a plurality of pixels in an image sensor pixel array;

a conductive line coupled to each of the plurality of pixels; and

analog-to-digital converter circuitry coupled to the plurality of pixels via the conductive line, the analog-to-digital converter circuitry having a first analog-to-digital converter coupled to the conductive line and a second analog-to-digital converter coupled to the conductive line using sample-and-hold circuitry, wherein the first analog-to-digital converter is configured to be selectively deactivated based on a pixel output signal passed onto the conductive line, and wherein the conductive line is connected to the second analog-to-digital converter when the first analog-to-digital converter is deactivated.

2. The image sensor defined in claim 1 wherein the first analog-to-digital converter is a ramp analog-to-digital converter.

3. The image sensor defined in claim 2 , wherein the second analog-to-digital converter is a successive approximation register analog-to-digital converter that includes the sample-and-hold circuitry.

4. The image sensor defined in claim 1 , wherein the plurality of pixels is a column of pixels in the image sensor pixel array, the conductive line is a column line coupling the column of pixels to column readout circuitry that includes the analog-to-digital converter circuitry.

5. The image sensor defined in claim 1 , wherein the analog-to-digital converter circuitry includes digital data processing circuitry coupled to a first output terminal of the first analog-to-digital converter and coupled to a second output terminal of the second analog-to-digital converter.

6. The image sensor defined in claim 5 , wherein the digital data processing circuitry is configured to:

receive first digital output data for a given image signal from the first analog-to-digital converter and second digital output data for the given image signal from the second analog-to-digital converter, and

generate final digital output data for the given image signal based on the first and second digital output data.

7. The image sensor defined in claim 5 , wherein the digital data processing circuitry includes an analog-to-digital converter output adjustment system that modifies at least one of the first or second digital output data based on respective transfer function characteristics of the first and second analog-to-digital converters.

8. The image sensor defined in claim 1 , further comprising:

a switch coupling the first analog-to-digital converter to the conductive line, wherein the switch is operable to connect the first analog-to-digital converter to the conductive line to activate the first analog-to-digital converter based on the pixel output signal being associated with a first conversion gain.

9. The image sensor defined in claim 8 , wherein the switch is operable to disconnect the first analog-to-digital converter from the conductive line to deactivate the first analog-to-digital converter based on the pixel output signal being associated with a second conversion gain less than the first conversion gain.

10. The image sensor defined in claim 9 , wherein the second analog-to-digital converter is configured to receive the pixel output signal when the first analog-to-digital converter is activated and when the first analog-to-digital converter is deactivated.

11. The image sensor defined in claim 1 , wherein the first analog-to-digital converter is configured to be selectively deactivated by disconnecting the first analog-to-digital converter from the conductive line based on a conversion gain of the pixel output signal.

12. An image sensor comprising:

an image sensor pixel array having first and second pixels in first and second corresponding rows of the image sensor pixel array and in a same column of the image sensor pixel array;

a column line coupled to the first and second pixels;

a first analog-to-digital converter selectively coupled to the column line; and

a second analog-to-digital converter coupled to the column line, the second analog-to-digital converter having a first capacitive digital-to-analog converter operable to perform a first conversion operation for the first pixel and a second capacitive digital-to-analog converter operable to perform a second conversion operation for the second pixel.

13. The image sensor defined in claim 12 , wherein the first analog-to-digital converter is a ramp analog-to-digital converter.

14. The image sensor defined in claim 13 , wherein the second analog-to-digital converter is a successive approximation register analog-to-digital converter.

15. The image sensor defined in claim 14 , wherein the successive approximation register analog-to-digital converter includes successive approximation register logic circuitry operable to control the first and second capacitive digital-to-analog converters.

16. A method of performing analog-to-digital conversion to generate image data comprising:

providing a pixel signal from an image sensor pixel to a pixel output path;

performing a first analog-to-digital conversion operation on the pixel signal using a ramp analog-to-digital converter based on a ramp signal;

performing a second analog-to-digital conversion operation on the pixel signal using an additional analog-to-digital converter after beginning the first analog-to-digital conversion operation;

providing an additional pixel signal from an additional image sensor pixel to the pixel output path; and

performing a third analog-to-digital conversion operation on the additional pixel signal using the ramp analog-to-digital converter while performing the second analog-to-digital conversion operation on the pixel signal using the additional analog-to-digital converter.

17. The method defined in claim 16 , wherein performing the first analog-to-digital conversion operation comprises performing the first analog-to-digital conversion operation during a settling time period for the pixel signal.

18. The method defined in claim 16 , further comprising:

providing a second additional pixel signal from the image sensor pixel to the pixel output path; and

performing a fourth analog-to-digital conversion operation on the second additional pixel signal using the additional analog-to-digital converter without using the ramp analog-to-digital converter to perform any analog-to-digital conversion operations on the second additional pixel signal.

19. The method defined in claim 18 , wherein the pixel signal is associated with a first conversion gain, and the second additional pixel signal is associated with a second conversion gain less than the first conversion gain.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL 055315, FRAME 0350 Recorded Aug 17, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064618/0881 →
SECURITY INTEREST Recorded Feb 17, 2021
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 055315/0350 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 28, 2020
From: YOUNG, BRIAN
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 054752/0767 →