Memory device interface and method
Apparatus and methods are disclosed, including memory devices and systems. In an example, a memory module can include a first stack of at least eight memory die including four pairs of memory die, each pair of the four pairs of memory die associated with an individual memory rank of four memory ranks of the memory module, a memory controller configured to receive memory access commands and to access memory locations of the first stack, and a substrate configured to route connections between external terminations of the memory module and the memory controller.
1. A memory module, comprising:
a first stack of at least nine memory die including four pairs of memory die, each pair of the four pairs of memory die associated with an individual memory rank of four memory ranks of the memory module;
a memory controller configured to receive memory access commands and to access memory locations of the first stack, wherein the memory controller is configured to store error correction code (ECC) information on a first memory die of the at least nine memory dies, and wherein the first memory die is not one of the four pairs of memory dies; and
a substrate configured to route connections between external terminations of the first stack of memory die and the memory controller.
2. The memory module of claim 1 , wherein the first stack includes at least ten memory dies;
wherein the memory controller is configured to store single device data correction (SDDC) information on a second memory die of the at least ten memory dies; and
wherein the second memory die is not one of the four pairs of memory dies.
3. The memory module of claim 1 , wherein the memory controller is mounted laterally offset from the first stack on the substrate.
4. The memory module of claim 1 , wherein the memory controller is mounted between the first stack and the substrate.
5. The memory module of claim 1 , including a plurality of wire bond terminations configured to couple terminations of the first stack with terminations of the substrate.
6. The memory module of claim 5 , wherein a first wire bond termination of the plurality of wire bond terminations is configured to couple a first, single, data termination of the substrate with a first data termination of at least four memory die of the first stack of eight memory dies.
7. The memory module of claim 1 , further comprising a second stack of at least eight memory dies, the second stack including a second four pairs of memory dies, each pair of the second four pairs of memory dies associated with an individual memory rank of the four memory ranks of the memory module.
8. The memory module of claim 7 , wherein the second stack is offset on the substrate from the first stack and from the memory controller.
9. The memory module of claim 7 , wherein the second stack is stacked with the first stack.
10. The memory module of claim 7 , wherein each rank includes at least four memory die of the memory dies forming the first and second stacks.
11. The memory module of claim 1 , wherein each memory die of the at least eight memory dies in the first stack is offset laterally from a neighboring memory die of the first stack to expose a wire bond termination area of at least seven of the at least eight memory dies.
12. An apparatus, comprising:
a first stack of at least eight memory die including four pairs of memory die, each pair of the four pairs of memory die associated with an individual memory rank of four memory ranks;
a memory controller configured to receive memory access commands and to access memory locations of the first stack; and
a substrate configured to route connections between external terminations of the first stack of memory die and the memory controller;
a buffer die coupled to the substrate, the buffer die including a host device interface, and a memory interface coupled to the first stack; and
circuitry in the buffer die, configured to operate the host interface at a first data speed, and to operate the memory interface at a second data speed, slower than the first data speed.
13. The apparatus of claim 12 , wherein the first stack includes dynamic random-access memory (DRAM) die.
14. The apparatus of claim 12 , wherein the first stack includes 8 dynamic random-access memory (DRAM) die.
15. The apparatus of claim 12 , wherein the first stack includes 9 dynamic random-access memory (DRAM) die.
16. The apparatus of claim 12 , wherein the first stack includes 10 dynamic random-access memory (DRAM) die.
17. The apparatus of claim 12 , wherein the first stack includes 16 dynamic random-access memory (DRAM) die.
18. The apparatus of claim 12 , wherein the first stack includes 18 dynamic random-access memory (DRAM) die.
19. The apparatus of claim 12 , wherein the first stack includes 20 dynamic random-access memory (DRAM) die.
20. The apparatus of claim 1 , wherein the first stack includes stair-stepped stacked memory dies.
21. The apparatus of claim 20 , wherein the first stack includes more than one step direction within a single stack.
22. A method, comprising:
storing information at memory cells of at least eight memory devices in a stack;
organizing the information across four ranks of memory cells, wherein each rank of the four ranks is assigned to at least two of the at least eight memory devices; and
storing error correction code (ECC) information on memory cells of a ninth memory device of the stack, wherein the ninth memory device is in addition to the at least eight memory devices.
23. The method of claim 22 , wherein the ninth memory device is assigned the ECC information for a single rank of the four ranks.
24. The method of claim 22 , including storing Single Device Data Correction (SDDC) information on memory cells of a tenth memory device of the stack, wherein the tenth memory device is in addition to the at least eight memory devices.