IP Library Granted Patent US 11,475,962
Granted Patent B2
US 11,475,962 · App. 17/137,547 · Granted Oct 18, 2022

Memory system performing read operation with read voltage

Inventor: Hiroyuki Nagashima (Yokohama, JP)
Assignee: Kioxia Corporation
G11C16/26G06F11/1048G11C11/5628G11C11/5642G11C16/14G11C16/24G11C16/34G11C16/3418G06F11/3466G06F2201/88G11C16/0483
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Quick Facts
Patent No.
US 11,475,962
App. No.
17/137,547
Granted
Oct 18, 2022
Kind
B2
Abstract

According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile semiconductor memory device includes a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to change a read level of the memory cell. The control unit controls write, read, and erase of the nonvolatile semiconductor memory device. The control unit changes the read level between a start of use of the nonvolatile semiconductor memory device and a timing after an elapse of a time.

Claims (28)

1. A memory system comprising:

a nonvolatile semiconductor memory device including a memory cell, and

a control circuit configured to:

cause the nonvolatile semiconductor memory device to execute a first read operation to the memory cell with a first voltage,

in a case where an error is detected after the first read operation, cause, the nonvolatile semiconductor memory device to execute a second read operation to the memory cell with a second voltage, the second voltage being different from the first voltage,

in a case where an error is not detected after the second read operation, record data related to the second voltage,

in a case where an error is detected after the second read operation, cause, the nonvolatile semiconductor memory device to execute a third read operation with a third voltage that is based on the recorded data related to the second voltage, the third voltage being different from the first voltage and the second voltage,

in a case where an error is not detected after the third read operation, record the data related to the third voltage.

2. The memory system of claim 1 , wherein:

the second voltage is higher than the first voltage, and

the third voltage is lower than the first voltage.

3. A method of memory system comprising a nonvolatile semiconductor memory device including a memory cell, the method comprising:

causing the nonvolatile semiconductor memory device to execute a first read operation to the memory cell with a first voltage,

in a case where an error is detected after the first read operation, causing, the nonvolatile semiconductor memory device to execute a second read operation to the memory cell with a second voltage, the second voltage being different from the first voltage,

in a case where an error is not detected after the second read operation, recording data related to the second voltage,

in a case where an error is detected after the second read operation, causing, the nonvolatile semiconductor memory device to execute a third read operation with a third voltage that is based on the recorded data related to the second voltage, the third voltage being different from the first voltage and the second voltage,

in a case where an error is not detected after the third read operation, recording the data related to the third voltage.

4. The method of claim 3 , wherein:

the second voltage is higher than the first voltage, and

the third voltage is lower than the first voltage.

5. The method of claim 3 , wherein the second voltage is higher or lower than the first voltage.

6. The method of claim 3 , wherein a time of the first read operation is different from a time of the second read operation.

7. The method of claim 6 , wherein the time of the first read operation is different from the time of the second read operation by one of changing a precharge voltage of a sense node of the memory cell and changing the number of times of sense.

8. The method of claim 6 , wherein a fourth voltage supplied to an unselected word line adjacent to a selected word line in the second read operation is higher than a fifth voltage supplied to the unselected word line in the first read operation.

9. The method of claim 3 , further comprising:

recording the data related to the second voltage in a case where the second voltage is set based on a standing time of the nonvolatile semiconductor memory device.

10. The method of claim 3 , further comprising:

recording the data related to the second voltage in a case where the second voltage is set based on at least one of a write count, an erase count, and a read count.

Assignments (2)
MERGER AND CHANGE OF NAME Recorded Jan 20, 2022
From: TOSHIBA MEMORY CORPORATION; K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 058785/0124 →
CHANGE OF NAME Recorded Jan 20, 2022
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 058785/0197 →
Cited By (1)
US 12,308,082