Semiconductor device package, electronic assembly and method for manufacturing the same

1. An electronic assembly, comprising:

a structure including a substrate and a protection layer encapsulating a first surface of the substrate, the protection layer and the substrate defining a first accommodating space; and

a first semiconductor device package partially inserted into the first accommodating space,

wherein the substrate further includes a second surface, and an area of the first surface is larger than an area of the second surface, and

wherein the first semiconductor device package includes a first surface and a second surface, an area of second surface is greater than an area of the first surface, and the first surface of the first semiconductor device package is inserted into the first accommodating space and faces the first surface of the substrate.

2. The electronic assembly of claim 1 , wherein the second surface of the first semiconductor device package is substantially vertical with respect to the first surface of the substrate.

3. The electronic assembly of claim 1 , wherein the second surface of the first semiconductor device package includes a first portion outside the first accommodating space and a second portion within the first accommodating space, and an area of the first portion is larger than an area of the second portion.

4. The electronic assembly of claim 1 , wherein the first semiconductor device package includes a carrier and an electronic component disposed on the carrier, the electronic component is electrically connected to the structure, and the first surface of the first semiconductor device package is a lateral surface of the carrier.

5. The electronic assembly of claim 4 , wherein the first semiconductor device package further includes an encapsulant encapsulating the electronic component, and the first surface of the first semiconductor device package is defined by the lateral surface of the carrier and the encapsulant.

6. An electronic assembly, comprising:

a structure including a substrate and a protection layer encapsulating a first surface of the substrate, the protection layer and the substrate defining a first accommodating space; and

a first semiconductor device package partially inserted into the first accommodating space,

wherein the structure further includes a conductive layer disposed on the substrate, and the first semiconductor device package is electrically connected to the conductive layer by a connection element, and

wherein the protection layer exposes a portion of the conductive layer, and the connection element covers the portion of the conductive layer.

7. The electronic assembly of claim 6 , wherein the connection element is at least partially disposed in the first accommodating space.

8. The electronic assembly of claim 7 , wherein the first semiconductor device package comprises a carrier and an electronic component disposed over the carrier, and the connection element is in contact with the conductive layer and the carrier.

9. The electronic assembly of claim 6 , wherein the connection element comprises a plurality of portions separated from each other, the plurality of portions of the connection element being connected to the conductive layer of the structure from a top view perspective.

10. The electronic assembly of claim 6 , wherein

the protection layer and the substrate further define a second accommodating space, and the electronic assembly further comprises a second semiconductor device package partially inserted into the second accommodating space,

the first semiconductor device package comprises a first carrier and a first connection element connecting the first carrier to the structure, and the second semiconductor device package comprises a second carrier and a second connection element connecting the second carrier to the structure, and

the first connection element is closer to the second connection element than the second carrier.

11. The electronic assembly of claim 10 , wherein the first semiconductor device package further comprises a first encapsulant partially encapsulating the first connection element, the second semiconductor device package further comprises a second encapsulant partially encapsulating the second connection element, and a distance between the first encapsulant and the second encapsulant is greater than a distance between the first connection element and the second connection element.

12. An electronic assembly, comprising:

a structure including a substrate and a protection layer encapsulating a first surface of the substrate, the protection layer and the substrate defining a first accommodating space; and

a first semiconductor device package partially inserted into the first accommodating space,

wherein the structure further includes a conductive layer disposed on the substrate, and the first semiconductor device package is electrically connected to the conductive layer by a connection element, and

wherein the connection element comprises a stepped portion defined by the conductive layer.

13. The electronic assembly of claim 6 , wherein the substrate and the protection layer are in contact with a lateral surface of the first semiconductor device package.

14. An electronic assembly, comprising:

a structure including a substrate and a protection layer encapsulating a first surface of the substrate, the protection layer and the substrate defining a first accommodating space; and

a first semiconductor device package partially inserted into the first accommodating space,

wherein the structure further comprises a conductive layer and a recess recessed from a top surface of the structure, the recess exposes a top surface of the conductive layer, and a depth of the recess is less than a depth of the first accommodating space with respect to the top surface of the structure.

15. The electronic assembly of claim 6 , wherein the protection layer includes a plurality of sidewalls, and the sidewalls of the protection layer and the first surface of the substrate collectively define the first accommodating space.

16. The electronic assembly of claim 15 , wherein a first gap exists between a first sidewall of the plurality of sidewalls of the protection layer and the first semiconductor device package.

17. The electronic assembly of claim 16 , wherein a second gap exists between a second sidewall of the plurality of sidewalls of the protection layer and the first semiconductor device package.