Three-dimensional memory device with three-dimensional phase-change memory
Three-dimensional (3D) memory devices with 3D phase-change memory (PCM) and methods for forming and operating the 3D memory devices are disclosed. In an example, a 3D memory device includes a first semiconductor structure including a substrate, an array of NAND memory cells above the substrate, and a first bonding layer above the array of NAND memory cells. The first bonding layer includes first bonding contacts. The 3D memory device also further includes a second semiconductor structure including a second bonding layer above the first bonding layer and including second bonding contacts, a peripheral circuit and an array of PCM cells above the second bonding layer, and a semiconductor layer above and in contact with the peripheral circuit. The 3D memory device further includes a bonding interface between the first and second bonding layers. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.
1. A three-dimensional (3D) memory device, comprising:
a first semiconductor structure comprising:
a substrate;
an array of NAND memory cells above the substrate; and
a first bonding layer above the array of NAND memory cells, the first bonding layer comprising a plurality of first bonding contacts;
a second semiconductor structure comprising:
a second bonding layer above the first bonding layer, the second bonding layer comprising a plurality of second bonding contacts;
a peripheral circuit and an array of phase-change memory (PCM) cells above the second bonding layer; and
a semiconductor layer above and in contact with the peripheral circuit; and
a bonding interface between the first bonding layer and the second bonding layer, wherein the first bonding contacts are in contact with the second bonding contacts at the bonding interface.
2. The 3D memory device of claim 1 , wherein the peripheral circuit is above or below the array of PCM cells.
3. The 3D memory device of claim 1 , further comprising a pad-out interconnect layer above the semiconductor layer.
4. The 3D memory device of claim 1 , wherein each PCM cell comprises a 3D XPoint memory cell.
5. The 3D memory device of claim 1 , wherein the first semiconductor structure further comprises a first interconnect layer between the first bonding layer and the array of PCM cells, and the second semiconductor structure further comprises a second interconnect layer between the second bonding layer and the array of NAND memory cells.
6. The 3D memory device of claim 5 , wherein the array of PCM cells are electrically connected to the array of NAND memory cells through the first and second interconnect layers and the first and second bonding contacts.
7. The 3D memory device of claim 1 , wherein the semiconductor layer comprises polysilicon.
8. The 3D memory device of claim 1 , wherein the semiconductor layer comprises single-crystal silicon.
9. The 3D memory device of claim 1 , wherein the peripheral circuit comprises a peripheral circuit of the array of NAND memory cells and a peripheral circuit of the array of PCM cells.
10. The 3D memory device of claim 1 , wherein the array of NAND memory cells comprises an array of 3D NAND memory strings.
11. A method for forming a three-dimensional (3D) memory device, comprising:
forming an array of NAND memory cells above a first substrate;
forming a first bonding layer above the array of NAND memory cells, the first bonding layer comprising a plurality of first bonding contacts;
forming a peripheral circuit and an array of phase-change memory (PCM) cells above a second substrate;
forming a second bonding layer above the peripheral circuit and the array of PCM cells, the second bonding layer comprising a plurality of second bonding contacts; and
bonding the first substrate and the second substrate in a face-to-face manner, such that the second substrate is above the first substrate after the bonding, and the first bonding contacts are in contact with the second bonding contacts at a bonding interface.
12. The method of claim 11 , further comprising:
thinning the second substrate to form a semiconductor layer after the bonding; and
forming a pad-out interconnect layer above the semiconductor layer.
13. The method of claim 11 , wherein forming the array of PCM cells comprises forming an array of 3D XPoint memory cells.
14. The method of claim 11 , wherein the peripheral circuit is formed above or below the array of PCM cells.
15. The method of claim 11 , wherein the bonding comprises hybrid bonding.
16. The method of claim 11 , wherein the peripheral circuit comprises a peripheral circuit of the array of NAND memory cells and a peripheral circuit of the array of PCM cells.
17. The method of claim 11 , wherein the array of NAND memory cells comprises an array of 3D NAND memory strings.