Method of manufacturing a semiconductor device and a semiconductor device
In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers containing Ge and second semiconductor layers are alternately stacked, is formed over a bottom fin structure. A Ge concentration in the first semiconductor layers is increased. A sacrificial gate structure is formed over the fin structure. A source/drain epitaxial layer is formed over a source/drain region of the fin structure. The sacrificial gate structure is removed. The second semiconductor layers in a channel region are removed, thereby releasing the first semiconductor layers in which the Ge concentration is increased. A gate structure is formed around the first semiconductor layers in which the Ge concentration is increased.
1. A semiconductor device, comprising:
semiconductor wires vertically arranged, each of which has a channel region;
a source/drain epitaxial layer connected to the semiconductor wires;
a gate structure formed around the semiconductor wires, wherein:
the semiconductor wires are made of Si 1-x Ge x , where 0.45≤x≤0.55; and
dielectric inner spacers disposed between the gate structure and the source/drain epitaxial layer.
2. The semiconductor device of claim 1 , wherein a width of the semiconductor wires is smaller than a thickness of the semiconductor wires.
3. The semiconductor device of claim 1 , wherein a thickness of the semiconductor wires is greater than a space between adjacent semiconductor wires.
4. The semiconductor device of claim 1 , wherein a cross section of the semiconductor wires has a dog-bone shape or a thread-spool shape.
5. The semiconductor device of claim 1 , wherein the semiconductor device is a p-channel field effect transistor.
6. The semiconductor device of claim 1 , wherein the source/drain epitaxial layer wraps around source/drain regions of the semiconductor wires.
7. The semiconductor device of claim 1 , further comprising gate sidewall spacers made of a different material than a material of the dielectric inner spacers.
8. The semiconductor device of claim 7 , wherein the material of the dielectric inner spacers is silicon nitride, and the material of the sidewall spacers is one of SiOC, SiCON and SiCN.
9. A semiconductor device, comprising:
an n-channel field effect transistor (FET); and
a p-channel FET, wherein:
the n-channel FET includes:
first semiconductor wires vertically arranged, each of which has a channel region;
a first source/drain epitaxial layer connected to the first semiconductor wires;
a first gate structure formed around the first semiconductor wires; and
first dielectric inner spacers disposed between the first gate structure and the first source/drain epitaxial layer,
the p-channel FET includes:
second semiconductor wires vertically arranged, each of which has a channel region; and
a second source/drain epitaxial layer connected to the second semiconductor wires,
the second semiconductor wires are made of Si 1-x Ge x , where 0.45≤x, and
the first semiconductor wires are made of Si or Si 1-y Ge y , where 0<y≤0.2.
10. The semiconductor device of claim 9 , wherein:
the second semiconductor wires are made of Si 1-x Ge x , where 0.45≤x≤0.55, and
the first semiconductor wires are made of Si.
11. The semiconductor device of claim 9 , wherein a width of the second semiconductor wires is smaller than a width of the first semiconductor wires.
12. The semiconductor device of claim 9 , wherein a width of the second semiconductor wires is smaller than a thickness of the first semiconductor wires and a thickness of the second semiconductor wires.
13. The semiconductor device of claim 9 , wherein:
the first source/drain epitaxial layer wraps around source/drain regions of the first semiconductor wires, and
the second source/drain epitaxial layer wraps around source/drain regions of the second semiconductor wires.
14. The semiconductor device of claim 9 , wherein the first source/drain epitaxial layer is formed on end faces of the first semiconductor wires.
15. The semiconductor device of claim 9 , wherein a cross section of the second semiconductor wires has a dog-bone shape or a thread-spool shape.
16. The semiconductor device of claim 15 , wherein a cross section of the first semiconductor wires has one of a rectangular shape with rounded corners and an oval shape.
17. A semiconductor device, comprising:
a first p-channel field effect transistor (FET); and
a second p-channel FET, wherein:
the first p-channel FET includes:
first semiconductor wires vertically arranged, each of which has a channel region;
a first source/drain epitaxial layer connected to the first semiconductor wires;
a first gate structure formed around the first semiconductor wires; and
first dielectric inner spacers disposed between the first gate structure and the first source/drain epitaxial layer,
the second p-channel FET includes:
second semiconductor wires and third semiconductor wires alternately stacked, each of which has a channel region;
a second source/drain epitaxial layer connected to the second and third semiconductor wires; and
a second gate structure formed around the second semiconductor wires,
the first and second semiconductor wires are made of Si 1-x Ge x , where 0.45≤x, and
the third semiconductor wires are made of Si or Si 1-y Ge y , where 0<y≤0.2.
18. The semiconductor device of claim 17 , wherein:
a cross section of the second semiconductor wires has a dog-bone shape or a thread-spool shape, and
a cross section of the first semiconductor wires has one of a rectangular shape with rounded corners and an oval shape.
19. The semiconductor device of claim 17 , wherein a width of the second semiconductor wires is smaller than a thickness of the first semiconductor wires and a thickness of the second semiconductor wires.
20. The semiconductor device of claim 17 , wherein the second p-channel FET further includes second dielectric inner spacers disposed between the second gate structure and the second source/drain epitaxial layer.