Crossing multi-stack nanosheet structure and method of manufacturing the same
A semiconductor device includes a substrate; a 1 st transistor formed above the substrate, and having a 1 st transistor stack including a plurality of 1 st channel structures, a 1 st gate structure surrounding the 1 st channel structures, and 1 st and 2 nd source/drain regions at both ends of the 1 st transistor stack in a 1 st channel length direction; and a 2 nd transistor formed above the 1 st transistor in a vertical direction, and having a 2 nd transistor stack including a plurality of 2 nd channel structures, a 2 nd gate structure surrounding the 2 nd channel structures, and 3 rd and 4 th source/drain regions at both ends of the 2 nd transistor stack in a 2 nd channel length direction, wherein the 3 rd source/drain region does not vertically overlap the 1 st source/drain region or the 2 nd source/drain region, and the 4 th source/drain region does not vertically overlap the 1 st source/drain region or the 2 nd source/drain region.
1. A semiconductor device comprising:
a substrate;
a 1 st transistor formed above the substrate, and having a 1 st transistor stack comprising a plurality of 1 st channel structures, a 1 st gate structure surrounding the 1 st channel structures, and 1 st and 2 nd source/drain regions at both ends of the 1 st transistor stack in a 1 st channel length direction; and
a 2 nd transistor formed above the 1 st transistor in a vertical direction, and having a 2 nd transistor stack comprising a plurality of 2 nd channel structures, a 2 nd gate structure surrounding the 2 nd channel structures, and 3 rd and 4 th source/drain regions at both ends of the 2 nd transistor stack in a 2 nd channel length direction,
wherein the 3 rd source/drain region vertically overlaps neither the 1 st source/drain region nor the 2 nd source/drain region, and the 4 th source/drain region vertically overlaps neither the 1 st source/drain region nor the 2 nd source/drain region, and
wherein the 2 nd channel structures of the 2 nd transistor stack substantially overlap the 1 st channel structures of the 1 st transistor stack in a vertical direction.
2. The semiconductor device of claim 1 further comprising:
a gate contact structure connected to at least the 1 st gate structure; and
1 st to 4 th source/drain contact structures extended straight downward from a metal layer to be connected the 1 st to 4 th source/drain regions, respectively.
3. The semiconductor device of claim 2 , wherein at least the 1 st and 2 nd source/drain contact structure land on top surfaces of the 1 st and 2 nd source/drain regions.
4. The semiconductor device of claim 1 , wherein the 2 nd transistor stack is a fin field-effect transistor (finFET) stack comprising a plurality of fin structures, and
wherein the 1 st transistor stack is a nanosheet stack comprising a plurality of nanosheet layers.
5. The semiconductor device of claim 1 , wherein a channel width of the 1 st channel structures is equal to a channel length of the 2 nd channel structures.
6. The semiconductor device of claim 1 , wherein the 1 st and 2 nd channel length directions are different from each other.
7. The semiconductor device of claim 1 , wherein a part of the 1 st gate structure is extended above the 1 st transistor stack to a side of the 2 nd transistor stack to be disposed next to the 2 nd gate structure.
8. A transistor structure comprising a 1 st transistor stack and a 2 nd transistor stack formed above the 1 st transistor stack,
wherein the 1 st transistor stack comprises a plurality of 1 st channel structures surrounded by a 1 st gate structure, and the 2 nd transistor stack comprises a plurality of 2 nd channel structures surrounded by a 2 nd gate structure,
wherein the 1 st channel structures are configured to form 1 st channels for a 1 st current flow in the 1 st channel length direction, and the 2 nd channel structures are configured to form 2nd channels for a 2 nd current flow in the 2 nd channel length direction, and
wherein the 1 st and 2 nd channel length directions are different from each other, and
wherein a channel width of the 1 st channel structures is equal to a channel length of the 2 nd channel structures.
9. The transistor structure of claim 8 , wherein the 1 st transistor stack is a 1 st nanosheet stack comprising a plurality of 1 st nanosheet layers, and
wherein the 2 nd transistor stack is a fin field-effect transistor (finFET) stack comprising a plurality of fin structures.
10. The transistor structure of claim 8 , wherein the 1 st transistor stack further comprises 1 st and 2 nd source/drain regions, and the 2 nd transistor stack further comprises 3 rd and 4 th source/drain regions, and
wherein the 3 rd source/drain region does not vertically overlap the 1 st source/drain region or the 2 nd source/drain region, and the 4 th source/drain region does not vertically overlap the 1 st source/drain region or the 2 nd source/drain region.
11. The transistor structure of claim 8 , wherein a part of the 1 st gate structure is extended above the 1 st transistor stack to a side of the 2 nd transistor stack to be disposed next to the 2 nd gate structure.
12. A method of manufacturing a semiconductor device, the method comprising operations of:
(a) providing a semiconductor device structure comprising a substrate, 1 st transistor stack formed on the substrate, and a 2 nd transistor stack formed on the 1 st transistor stack, wherein the 1 st and 2 nd transistor stacks comprise a plurality of 1 st and 2 nd channel structures, respectively;
(b) forming a 1 st dummy gate to surround the 1 st transistor stack, and forming a 2 nd dummy gate on the 1 st dummy gate to surround the 2 nd transistor stack and a top surface of the 2 nd transistor stack;
(c) removing the 1 st dummy gate on at least parts of at least 1 st and 2 nd sides among four sides of the 1 st transistor stack, and forming 1 st and 2 nd source/drain regions on the 1 st and 2 nd sides of the 1 st transistor stack, respectively, where the 1 st dummy gate is removed;
(d) removing the 2 nd dummy gate on at least parts of at least 3 rd and 4 th sides among four sides of the 2 nd transistor stack, and forming 3 rd and 4 th source/drain regions on the 3 rd and 4 th sides of the 2 nd transistor stack, respectively, where the 2 nd dummy gate is removed; and
(e) removing and replacing the remaining 1 st and 2 nd dummy gates with 1 st and 2 nd replacement metal gates, respectively, to form 1 st and 2 nd gate structures surrounding the 1 st and 2 nd channel structures, respectively,
wherein the 1 st to 4 th source/drain regions are formed such that the 3 rd source/drain region does not overlap the 1 st source/drain region or the 2 nd source/drain region, and the 4 th source/drain region does not overlap the 1 st source/drain region or the 2 nd source/drain region.
13. The method of claim 12 , further comprising:
(f) forming a gate contact structure on the 2 nd gate structure; and
(g) forming 1 st to 4 th source/drain contact structures to land on the 1 st to 4 th source/drain regions, respectively,
wherein the 1 st and 2 nd source/drain contact structures are not bent to be connected to the 1 st and 2 nd source/drain regions, or do not land on side surfaces of the 1 st and source/drain regions, respectively.
14. The method of claim 13 , in operation (g), at least the 1 st and 2 nd source/drain contact structures are formed to land on top surfaces of the 1 st and 2 nd source/drain regions, respectively.
15. The method of claim 12 , wherein operation (e) comprises:
(e-1) removing and replacing the remaining 1 st dummy gate with the 1 st replacement metal gate to form the 1 st gate structure for the 1 st transistor stack; and
(e-2) after operation (e-1), removing and replacing the remaining 2 st dummy gate with the 2 nd replacement metal gate to form the 2 nd gate structure for the 2 nd transistor stack.
16. The method of claim 15 ,
wherein, in operation (c), the 1 st dummy gate is removed at a part of each of the at least the 1 st and 2 nd sides of the 1 st transistor stack, and
wherein, in operation (d), the 2 nd dummy gate is removed at a part of each of the at least the 3 rd and 4 th sides of the 2 nd transistor stack.
17. The method of claim 16 , wherein operation (d) is performed prior to operation (c), and
wherein, after the 2 nd dummy gate is removed at the part of each of the at least the 3 rd and 4 th sides of the 2 nd transistor stack, at least one edge area of the 2 nd dummy gate remains without being removed.
18. The method of claim 17 , wherein operation (e) comprises:
(e-1) forming a hole at one of the at least one edge area of the 2 nd dummy gate to expose the 1 st dummy gate though the hole;
(e-2) removing the remaining 1 st dummy gate though the hole; and
(e-3) forming the 1 st replacement metal gate through the hole.
19. The method of claim 18 , further comprising:
(e-4) forming the 1 st replacement metal gate in the hole; and
(e-5) connecting the 1 st replacement metal gate formed at the hole with the 2 nd replacement metal gate.
20. The method of claim 16 , wherein operation (d) is performed prior to operation (c), and
wherein, in operation (d), the 2 nd dummy gate is removed at a part of four sides including the 3 rd and 4 th sides of the 2 nd transistor stack, and four edge areas of the 2 nd dummy gate remain without being removed.