Stacked FET sidewall strap connections between gates
A set of stacked transistors, system, and method to connect the gates of stacked field-effect transistors through sidewall straps. The set of stacked transistors may include a first transistor including a first gate. The set of stacked transistors may also include a second transistor including a second gate, where the second transistor is above the first transistor. The set of stacked transistors may also include a dielectric preventing direct contact between the first gate and the second gate. The set of stacked transistors may also include a first sidewall strap proximately connected to the first gate and the second gate, where the first sidewall strap connects the first transistor and the second transistor.
1. A set of stacked transistors, the stacked transistors comprising:
a first transistor comprising a first gate;
a second transistor comprising a second gate, wherein the second transistor is above the first transistor;
a dielectric preventing direct contact between the first gate and the second gate; and
a first sidewall strap directly connected to the first gate and to the second gate to provide an electrical path between the first gate and the second gate, wherein the first sidewall strap connects the first transistor and the second transistor.
2. The stacked transistors of claim 1 , further comprising:
a second sidewall strap connecting the first transistor and the second transistor, wherein:
the first sidewall strap is directly connected to a first side of the first gate and a first side of the second gate, and
the second sidewall strap is directly connected to a second side of the first gate and a second side of the second gate.
3. The stacked transistors of claim 1 , wherein the first sidewall strap is a metal strap including at least one of TiN and W.
4. The stacked transistors of claim 1 , wherein:
the first transistor comprises a first channel; and
the second transistor comprises a second channel.
5. The stacked transistors of claim 4 , further comprising:
an insulating material separating the first channel from the second channel.
6. The stacked transistors of claim 1 , wherein the first transistor and the second transistor include at least one of finFETs and nanosheet transistors.
7. The stacked transistors of claim 1 , wherein the first transistor and the second transistor include an NFET and a PFET.
8. A system comprising:
first stacked transistors, the first stacked transistors comprising:
a first transistor comprising a first gate;
a second transistor comprising a second gate, wherein the second transistor is above the first transistor;
a dielectric preventing direct contact between the first gate and the second gate; and
a first sidewall strap directly connected to the first gate and to the second gate to provide an electrical path between the first gate and the second gate, wherein the first sidewall strap connects the first transistor and the second transistor.
9. The system of claim 8 , wherein the first stacked transistors further comprise:
a second sidewall strap connecting the first transistor and the second transistor, wherein:
the first sidewall strap is directly connected to a first side of the first gate and a first side of the second gate, and
the second sidewall strap is directly connected to a second side of the first gate and a second side of the second gate.
10. The system of claim 9 , further comprising:
second stacked transistors comprising a third transistor and a fourth transistor, wherein the second stacked transistors comprise a single sidewall strap connecting the third transistor and the fourth transistor.
11. The system of claim 9 , further comprising:
second stacked transistors comprising a third transistor and a fourth transistor, wherein the second stacked transistors are non-sidewall strap stacked transistors.
12. The system of claim 10 , further comprising:
third stacked transistors comprising a fifth transistor and a sixth transistor, wherein the third stacked transistors comprise a single sidewall strap connecting the fifth transistor and the sixth transistor.
13. The system of claim 8 , wherein the first transistor and the second transistor include at least one of finFETs and nanosheet transistors.
14. A method of forming stacked transistors with sidewall straps, the method comprising:
forming a first semiconductor and a second semiconductor separated by an insulator layer;
shaping the first semiconductor and the second semiconductor into a first channel and a second channel;
forming a first gate;
depositing a dielectric layer on top of the first gate;
forming a second gate on top of the dielectric layer, wherein the dielectric layer separates the first gate from the second gate; and
forming a first sidewall strap directly connected to the first gate and to the second gate to provide an electrical path between the first gate and the second gate.
15. The method of claim 14 , further comprising:
forming a second sidewall strap proximately connected to the first gate and the second gate.
16. The method of claim 15 , further comprising:
masking the first sidewall strap and the second sidewall strap to prevent removal of the first sidewall strap and the second sidewall strap.
17. The method of claim 15 , further comprising:
masking the first sidewall strap to prevent removal of the first sidewall strap; and
removing the second sidewall strap.
18. The method of claim 14 , further comprising:
depositing a high-k dielectric around at least portions of the first channel and the second channel.
19. The method of claim 14 , further comprising:
growing a bottom epitaxial proximately connected to the first channel; and
growing a top epitaxial proximately connected to the second channel.
20. The method of claim 14 , wherein the first sidewall strap is a metal strap including at least one of TiN and TiAlC.