Three-dimensional NAND memory device and method of forming the same

1. A semiconductor device, comprising:

a base layer having a first side for forming memory cells and a second side that is opposite to the first side;

a stack of alternating word line layers and insulating layers positioned over the first side of the base layer, the stack including a first region and a second region;

a channel structure extending through the first region of the stack along a vertical direction and further extending into the base layer;

a plurality of connection structures formed over the second side of the base layer and including a first connection structure that is coupled to the channel structure; and

a plurality of bonding pad contacts that each extend in the vertical direction as a single element from a first dielectric layer formed over the second side of the base layer, through a second dielectric layer arranged in the base layer between the first side and the second side, a third dielectric layer formed over a first surface of the second dielectric layer and the first side of the base layer, and the base layer.

2. The semiconductor device of claim 1 , further comprising:

a doped region formed in the second side of the base layer and coupled to the channel structure,

wherein the connection structures extend through the first dielectric layer so that the first connection structure of the connection structures is in direct contact with the doped region.

3. The semiconductor device of claim 2 , wherein:

the stack is arranged in the third dielectric layer, and

the plurality of bonding pad contacts are formed in the second dielectric layer and the third dielectric layer, the bonding pad contacts extending in the vertical direction between a second surface of the second dielectric layer and a top surface of the third dielectric layer.

4. The semiconductor device of claim 3 , wherein the connection structures further include a second connection structure that is coupled to the bonding pad contacts.

5. The semiconductor device of claim 4 , wherein the second region of the stack has a stair-cased configuration and the semiconductor device further comprises:

a plurality of word line contacts that are formed in the third dielectric layer and positioned on respective word line layers in the second region.

6. The semiconductor device of claim 5 , wherein the connection structures further include a third connection structure and the semiconductor device further comprises:

a gate line slit structure that extends through the third dielectric layer in the vertical direction and extends into the base layer, and further is coupled to the third connection structure of the connection structures.

7. The semiconductor device of claim 6 , further comprising:

a source layer that is positioned between the base layer and the stack, and surrounds a bottom channel contact of the channel structure.

8. The semiconductor device of claim 7 , further comprising:

a substrate having a first side and an opposing second side;

a transistor formed in the first side of the substrate; and

a plurality of contact structures extending from the first side of the substrate in the vertical direction, one of the contact structures being coupled to the transistor.

9. The semiconductor device of claim 8 , further comprising:

first bonding structures formed over the top surface of the third dielectric layer and coupled to the bonding pad contacts, the word line contacts, and a top channel contact of the channel structure; and

second bonding structures formed over the contact structures and coupled to the contact structures,

wherein the first side of the substrate and the first side of the base layer are aligned facing each other so that the first bonding structures and the second bonding structures are connected to each other.

10. A semiconductor device, comprising:

a transistor formed in a first side of a substrate;

an memory cell structure formed over a first side of a base layer; and

a plurality of connection structures formed over an opposing second side of the base layer, wherein the memory cell structure includes:

a stack of alternating word line layers and insulating layers positioned over the first side of the base layer, the stack including a first region and a second region,

a channel structure extending through the first region of the stack in a vertical direction and further extending into the base layer,

a plurality of word line contacts extending from respective word line layers in the second region of the stack, the second region of the stack having a stair-cased configuration, and

a plurality of bonding pad contacts that extend in the vertical direction as a single element from a first dielectric layer formed over the second side of the base layer, through a second dielectric layer arranged in the base layer between the first side and the second side, a third dielectric layer formed over a first surface of the second dielectric layer and the first side of the base layer, and the base layer,

wherein:

the connection structures include a first connection structure that is coupled to the channel structure, and

the first side of the substrate and the first side of the base layer face each other so that the transistor and the channel structure are coupled to each other.

11. The semiconductor device of claim 10 , further comprises:

a doped region formed in the second side of the base layer and coupled to the channel structure,

wherein the connection structures extend through the first dielectric layer so that the first connection structure of the connection structures is in direct contact with the doped region.

12. The semiconductor device of claim 11 , wherein:

the stack is arranged in the third dielectric layer, and

the plurality of bonding pad contacts are formed in the second dielectric layer and the third dielectric layer, the bonding pad contacts extending in the vertical direction between a second surface of the second dielectric layer and a top surface of the third dielectric layer.

13. The semiconductor device of claim 12 , further comprises:

a plurality of contact structures extending from the first side of the substrate in the vertical direction, wherein:

a first contact structure of the contact structures is coupled to the transistor and further coupled to one of the word line contacts, and

a second contact structure of the contact structures is coupled to one of the bonding pad contacts.