Three-dimensional NAND memory device and method of forming the same
A semiconductor device is provided. The semiconductor device includes a base layer having a first side for forming memory cells and a second side that is opposite to the first side. The semiconductor device includes a stack of alternating word line layers and insulating layers that is positioned over the first side of the base layer, where the stack includes a first region and a second region. A channel structure extends through the first region of the stack in a vertical direction and further extends into the base layer from the first side. A plurality of connection structures are formed over the second side of the base layer and include a first connection structure that is coupled to the channel structure.
1 . A semiconductor device, comprising:
a base layer comprising a first semiconductor layer and a second semiconductor layer stacked along a first direction;
a stack of alternating conductive layers and insulating layers positioned over a first side of the base layer;
a pad contact structure extending along the first direction in a third dielectric layer, wherein the third dielectric layer is disposed at a side of the stack in a second direction perpendicular to the first direction;
a connection structure comprising a second connection structure coupled to the pad contact structure, wherein at least a part of the connection structure is over a second side of the base layer opposite to the first side of the base layer;
a channel structure comprising a barrier layer, a charge trapping layer surrounded by the barrier layer, a tunneling layer surrounded by the charge trapping layer, and a channel layer surrounded by the tunneling layer, wherein the channel structure extends through the stack along the first direction into the base layer; and
a second dielectric layer in the base layer, wherein a part of the second connection structure is over and in contact with the second dielectric layer,
wherein the first semiconductor layer of the base layer extends through a portion of the barrier layer, the charge trapping layer, and the tunneling layer of the channel structure, and is connected to the channel layer of the channel structure.
2 . The semiconductor device of claim 1 , wherein the pad contact structure extends through the second dielectric layer.
3 . The semiconductor device of claim 1 , further comprising:
a first dielectric layer over the second side of the base layer, wherein the connection structure further comprises a first connection structure extending through the first dielectric layer and connecting with the base layer.
4 . The semiconductor device of claim 3 , wherein the second connection structure extends through the first dielectric layer in the first direction, and the first dielectric layer and the second dielectric layer isolate the second connection structure from the base layer.
5 . The semiconductor device of claim 1 , further comprising:
a source layer arranged between the base layer and the stack, and surrounding the channel structure.
6 . The semiconductor device of claim 1 , further comprising:
a contact structure in the third dielectric layer and coupled to a corresponding conductive layer.
7 . The semiconductor device of claim 1 , further comprising:
a slit structure that extends through the stack in the first direction into the base layer.
8 . The semiconductor device of claim 1 , further comprising:
a substrate;
a transistor formed over the substrate; and
a contact structure coupled to the transistor and connected to the pad contact structure.
9 . The semiconductor device of claim 8 , wherein the third dielectric layer having a first surface away from the second dielectric layer, the semiconductor device further comprising:
a first bonding structure arranged over the first surface of the third dielectric layer and coupled to the pad contact structure; and
a second bonding structure arranged over the contact structure and coupled to the contact structure,
wherein the first bonding structure and the second bonding structure are connected to each other.
10 . The semiconductor device of claim 1 , wherein the pad contact structure extends through the second dielectric layer and the third dielectric layer.
11 . The semiconductor device of claim 1 , wherein:
a size of the pad contact structure near the connection structure is smaller than the size of the pad contact structure away from the connection structure.
12 . The semiconductor device of claim 1 , wherein a recess is arranged in the second connection structure at a side of the second connection structure away from the pad contact structure.
13 . A semiconductor device, comprising:
a base layer;
a stack of alternating conductive layers and insulating layers positioned over a first side of the base layer:
a pad contact structure extending along a first direction in a third dielectric layer, wherein the third dielectric layer is disposed at a side of the stack in a second direction perpendicular to the first direction;
a connection structure over a second side of the base layer opposite to the first side of the base layer, wherein the connection structure comprises a first connection structure coupled to the base layer and a second connection structure coupled to the pad contact structure, and the first connection structure and the second connection structure comprise grooves; and
a second dielectric layer arranged in the base layer, wherein a part of the second connection structure is over and in contact with the second dielectric layer.
14 . The semiconductor device of claim 13 , wherein the base layer comprises a first semiconductor layer and a second semiconductor layer stacked along the first direction, a first part of the first and second semiconductor layers is over the third dielectric layer, a second part of the first and second semiconductor layers is over the stack.
15 . The semiconductor device of claim 14 , further comprising:
a channel structure extending through the stack and the first semiconductor layer along the first direction and further extending into the second semiconductor layer;
wherein:
the channel structure comprises a barrier layer, a charge trapping layer surrounded by the barrier layer, a tunneling layer surrounded by the charge trapping layer, and a channel layer surrounded by the tunneling layer; and
the first semiconductor layer extends through a portion of the barrier layer, the charge trapping layer, and the tunneling layer, and is connected with the channel layer.
16 . The semiconductor device of claim 14 , further comprising:
a slit structure that extends through the stack and the first semiconductor layer in the first direction into the second semiconductor layer.
17 . The semiconductor device of claim 13 , further comprising:
a first dielectric layer over the second side of the base layer, wherein the first connection structure extends through the first dielectric layer and connects with the base layer.
18 . The semiconductor device of claim 13 , further comprising:
a substrate;
a transistor formed over of the substrate; and
a contact structure coupled to the transistor and connected to the pad contact structure.
19 . The semiconductor device of claim 18 , further comprising:
a first bonding structure over a first surface of the third dielectric layer and coupled to the pad contact structure; and
a second bonding structure arranged over the contact structure and coupled to the contact structure,
wherein the first bonding structure and the second bonding structure are connected to each other.
20 . The semiconductor device of claim 13 , wherein the pad contact structure extends through the second dielectric layer and the third dielectric layer.