Memory controller configured to transmit interrupt signal if volatile memory has no data corresponding to address requested from source
According to one embodiment, a memory device includes a nonvolatile memory, a volatile memory, a controller, and a board. The nonvolatile memory stores data. The volatile memory holds a part of the data stored in the nonvolatile memory. The memory controller controls the volatile memory and the nonvolatile memory. The nonvolatile memory, the volatile memory, and the memory controller are provided on the board. The memory controller transmits an interrupt signal to a request source, when the volatile memory does not have any data corresponding to an address which the request source requests to access.
1. A memory system comprising:
a nonvolatile memory configured to store data;
a volatile memory configured to store a part of the data stored in the nonvolatile memory, a capacity of the volatile memory being smaller than a capacity of the nonvolatile memory; and
a controller configured to:
in response to receiving, from a requester, a first request that includes an address,
send, to the requester, first information as to whether first data is not stored in the volatile memory, the first data corresponding to the address included in the first request.
2. The memory system according to claim 1 , wherein
the controller is configured to:
send the first information as an interrupt signal.
3. The memory system according to claim 1 , wherein
the controller is further configured to:
in response to receiving the first request from the requester,
in a case where the first data is stored in the volatile memory, send, to the requester, the first data from the volatile memory.
4. The memory system according to claim 1 , wherein
the controller is further configured to:
in response to receiving the first request from the requester,
in a case where the first data is not stored in the volatile memory,
read the first data from the nonvolatile memory; and
store the read first data into the volatile memory.
5. The memory system according to claim 4 , wherein
the controller is further configured to:
upon the first data being stored into the volatile memory, send, to the requester, second information indicating that the first data has been stored into the volatile memory.
6. The memory system according to claim 5 , wherein
the controller is further configured to:
after sending the second information to the requester, send, to the requester, the first data from the volatile memory.
7. The memory system according to claim 5 , further comprising:
a first pin and a second pin, the second pin being different from the first pin, wherein
the first information is sent to the requester through the first pin, and
the second information is sent to the requester through the second pin.
8. The memory system according to claim 1 , wherein
the controller is further configured to:
allow the requester to recognize that the memory system has a capacity equal to the capacity of the nonvolatile memory.
9. The memory system according to claim 1 , further comprising:
a dual inline memory module (DIMM) board, wherein
the nonvolatile memory, the volatile memory, and the controller are provided on the DIMM board.
10. The memory system according to claim 1 , wherein
the volatile memory comprises a dynamic random access memory (DRAM), and
the nonvolatile memory comprises a flash memory.
11. A memory system comprising:
a nonvolatile memory configured to store data;
a volatile memory configured to store a part of the data stored in the nonvolatile memory; and
a controller configured to:
in response to receiving, from a requester, a first request that includes an address,
in a case where first data is not stored in the volatile memory, the first data corresponding to the address included in the first request,
read the first data from the nonvolatile memory;
store the read first data into the volatile memory; and
upon the first data being stored into the volatile memory, send, to the requester, first information indicating that the first data has been stored into the volatile memory.
12. The memory system according to claim 11 , wherein
the controller is further configured to:
after sending the first information to the requester, send, to the requester, the first data from the volatile memory.
13. The memory system according to claim 11 , wherein
the controller is further configured to:
in response to receiving the first request from the requester,
in a case where the first data is stored in the volatile memory, send, to the requester, the first data from the volatile memory.
14. The memory system according to claim 11 , wherein
the controller is further configured to:
before sending the first information to the requester after receiving the first request, send, to the requester, second information as to whether the first data is not stored in the volatile memory.
15. The memory system according to claim 14 , wherein
the controller is configured to send the second information as an interrupt signal.
16. The memory system according to claim 14 , further comprising:
a first pin and a second pin, the second pin being different from the first pin, wherein
the first information is sent to the requester through the first pin, and
the second information is sent to the requester through the second pin.
17. The memory system according to claim 11 , wherein
a capacity of the volatile memory is smaller than a capacity of the nonvolatile memory, and
the controller is further configured to:
allow the requester to recognize that the memory system has a capacity equal to the capacity of the nonvolatile memory.
18. The memory system according to claim 11 , further comprising:
a dual inline memory module (DIMM) board, wherein
the nonvolatile memory, the volatile memory, and the controller are provided on the DIMM board.
19. The memory system according to claim 11 , wherein
the volatile memory comprises a dynamic random access memory (DRAM), and
the nonvolatile memory comprises a flash memory.
20. The memory system according to claim 11 , wherein
the requester is a central processing unit of an information processing device.