Coarse-fine counting architecture for a VCO-ADC based on interlocked binary asynchronous counters

1. An analog-to-digital converter (ADC) comprising:

a voltage-controlled oscillator (VCO) having an input for receiving an analog input signal, and having a plurality of outputs;

a double binary counter having a first input coupled to a first output of the plurality of outputs of the VCO, a second input coupled to a second output of the plurality of outputs of the VCO, a first output, and a second output;

a first plurality of registers coupled to the first output of the double binary counter;

a second plurality of registers coupled to the second output of the double binary counter;

a plurality of sense amplifiers coupled to the plurality of outputs of the VCO;

a correction component coupled to the first plurality of registers, the second plurality of registers, and the plurality of sense amplifiers, the correction component being configured to generate a coarse count, to generate a fine count, and to combine the coarse count and the fine count to provide a digital output signal representative of the analog input signal; and

a phase reordering circuit interposed between the plurality of sense amplifiers and the correction component.

2. The ADC of claim 1 , wherein the correction component is configured to generate the coarse count based on signals provided by the first plurality of registers and the second plurality of registers.

3. The ADC of claim 1 , wherein the correction component is configured to generate the fine count based on signals provided by the plurality of sense amplifiers.

4. The ADC of claim 1 , wherein the double binary counter comprises a first asynchronous counter and a second asynchronous counter.

5. The ADC of claim 4 , wherein at least one of the first asynchronous counter and the second asynchronous counter comprises a plurality of serially-connected D-type flip-flops.

6. The ADC of claim 4 , wherein the first asynchronous counter comprises a plurality of serially-connected D-type flip-flops and at least one internal node coupled to at least one internal node of the second asynchronous counter.

7. The ADC of claim 1 , wherein the first plurality of registers are configured for sampling the first output of the double binary counter, and wherein the second plurality of registers are configured for sampling the second output of the double binary counter.

8. The ADC of claim 1 , wherein the first plurality of registers, the second plurality of registers, the plurality of sense amplifiers, and the correction component each comprise a clock input for receiving a clock signal.

9. The ADC of claim 8 , wherein a clock frequency of the clock signal is less than a rest frequency of the VCO.

10. A converter comprising:

a plurality of sense amplifiers having a plurality of phase signal inputs;

a double binary counter having a first input coupled to a first phase signal input of the plurality of sense amplifiers and a second input coupled to a second phase signal input of the plurality of sense amplifiers;

a first plurality of registers coupled to a first output of the double binary counter;

a second plurality of registers coupled to a second output of the double binary counter;

a correction component coupled to the first plurality of registers, the second plurality of registers, and the plurality of sense amplifiers, the correction component being configured to generate a coarse count, to generate a fine count, and to combine the coarse count at a digital output; and

a phase reordering circuit interposed between the plurality of sense amplifiers and the correction component.

11. The converter of claim 10 , wherein the double binary counter comprises a first asynchronous counter and a second asynchronous counter.

12. The converter of claim 11 , wherein the first asynchronous counter comprises at least one internal node coupled to at least one internal node of the second asynchronous counter.

13. The converter of claim 10 , further comprising a phase reordering circuit interposed between the plurality of sense amplifiers and the correction component.

14. A method comprising:

generating a plurality of phase signals having a frequency dependent upon an analog input signal;

using a double binary counter having a first asynchronous counter and a second asynchronous counter to generate a first count from a first phase signal of the plurality of phase signals and to generate a second count from a second phase signal of the plurality of phase signals;

coupling an internal node of the first asynchronous counter to an internal node of the second asynchronous counter:

sampling the first count and the second count to generate a first plurality of sampled signals;

sampling the plurality of phase signals to generate a second plurality of sampled signals;

generating a coarse count in response to the first plurality of sampled signals;

generating a fine count in response to the second plurality of sampled signals; and

combining the coarse count and the fine count to generate a digital output signal.

15. The method of claim 14 , further comprising reordering the second plurality of sampled signals before generating the fine count.

16. The method of claim 14 , wherein generating the plurality of phase signals comprises generating the plurality of phase signals with a voltage-controlled oscillator (VCO).

17. The method of claim 14 , wherein sampling the first count and the second count and sampling the plurality of phase signals is performed at a sampling rate frequency less than a rest frequency of the plurality of phase signals.

18. An analog-to-digital converter (ADC) comprising:

a voltage-controlled oscillator (VCO) having an input for receiving an analog input signal, and having a plurality of outputs;

a double binary counter having a first input coupled to a first output of the plurality of outputs of the VCO, a second input coupled to a second output of the plurality of outputs of the VCO, a first output, and a second output;

a first plurality of registers coupled to the first output of the double binary counter;

a second plurality of registers coupled to the second output of the double binary counter;

a plurality of sense amplifiers coupled to the plurality of outputs of the VCO; and

a correction component coupled to the first plurality of registers, the second plurality of registers, and the plurality of sense amplifiers, the correction component being configured to generate a coarse count, to generate a fine count, and to combine the coarse count and the fine count to provide a digital output signal representative of the analog input signal,

wherein the double binary counter comprises a first asynchronous counter and a second asynchronous counter, and wherein the first asynchronous counter comprises at least one internal node coupled to at least one internal node of the second asynchronous counter.

19. A converter comprising:

a plurality of sense amplifiers having a plurality of phase signal inputs;

a double binary counter having a first input coupled to a first phase signal input of the plurality of sense amplifiers and a second input coupled to a second phase signal input of the plurality of sense amplifiers;

a first plurality of registers coupled to a first output of the double binary counter;

a second plurality of registers coupled to a second output of the double binary counter; and

a correction component coupled to the first plurality of registers, the second plurality of registers, and the plurality of sense amplifiers, the correction component being configured to generate a coarse count, to generate a fine count, and to combine the coarse count at a digital output,

wherein the double binary counter comprises a first asynchronous counter and a second asynchronous counter, and wherein the first asynchronous counter comprises at least one internal node coupled to at least one internal node of the second asynchronous counter.