IP Library Granted Patent US 11,711,916
Granted Patent B2
US 11,711,916 · App. 17/161,685 · Granted Jul 25, 2023

Method of forming semiconductor memory device

Inventors: Yi-Wei Chen (Taichung, TW); Hsu-Yang Wang (Tainan, TW); Chun-Chieh Chiu (Keelung, TW); Shih-Fang Tzou (Tainan, TW)
Assignees: UNITED MICROELECTRONICS CORP.; Fujian Jinhua Integrated Circuit Co., Ltd.
H10B12/485H01L21/76804H01L21/76805H01L21/76814H01L21/76819H01L21/76895H10B12/053H10B12/482
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Quick Facts
Patent No.
US 11,711,916
App. No.
17/161,685
Granted
Jul 25, 2023
Kind
B2
Abstract

A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.

Claims (17)

1. A method of forming a semiconductor memory device, comprising: providing a substrate;

forming a plurality of gates in the substrate, extending along a first direction;

forming a semiconductor layer on the substrate, covering the plurality of gates;

forming a protection layer on the semiconductor layer;

forming a plug in the semiconductor layer, between two adjacent gates of the plurality of gates,

wherein the forming of the plug comprises:

forming a plug-hole in the semiconductor layer;

forming a conductive layer on the semiconductor layer to fill in the plug-hole; and

forming a sacrificial layer entirely covering on the conductive layer and the plug-hole; and

performing an etching process to remove the sacrificial layer and the conductive layer on the semiconductor layer to form an arched top surface of the conductive layer;

performing a deposition process to from a stacked structure on the semiconductor layer; and

patterning the stacked structure to form a plurality of bit lines, with one of the bit lines directly in contact with the plug;

wherein the etching process comprises:

a first etching process, removing a portion of the sacrificial layer to expose a top surface of the conductive layer, to remain a rest portion of the sacrificial layer with a coplanar surface with the top surface of the conductive layer;

a second etching process, completely removing the sacrificial layer and the conductive layer on the semiconductor layer to expose the arched top surface of the conductive layer; and

a third etching process to remove the protection layer and the arched top surface of the conductive layer to form a planar top surface of the conductive layer coplanar with a top surface of the semiconductor layer.

2. The method of forming a semiconductor memory device according to claim 1 , wherein the etching process is performed by using an etchant which has a same etching selectivity related to the sacrificial layer and the conductive layer.

Priority Claims (1)
CN 201810425155.8 · May 7, 2018 · national
Continuity (2)
Division 16001949 · Jun 7, 2018
Related Publication 20210151442A1 · May 20, 2021