IP Library Granted Patent US 11,508,766
Granted Patent B2
US 11,508,766 · App. 17/162,014 · Granted Nov 22, 2022

Molded image sensor chip scale packages and related methods

Inventor: Weng-Jin Wu (Hsinchu, TW)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L27/14618H01L23/3114H01L27/14636H01L27/14685H01L27/14687H01L27/14698H01L2224/11
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Quick Facts
Patent No.
US 11,508,766
App. No.
17/162,014
Granted
Nov 22, 2022
Kind
B2
Abstract

Implementations of a molded image sensor chip scale package may include an image sensor having a first side and a second side. A first cavity wall and a second cavity wall may be coupled to the first side of the image sensor and extend therefrom. The first cavity wall and the second cavity wall may form a cavity over the image sensor. A transparent layer may be coupled to the first cavity wall and the second cavity wall. A redistribution layer (RDL) may be coupled to the second side of the image sensor. At least one interconnect may be directly coupled to the RDL. A mold material may encapsulate a portion of the RDL, a portion of the image sensor, and a side of each cavity wall, and a portion of the transparent layer.

Claims (32)

1. A method of forming a chip scale package, the method comprising:

providing a wafer comprising a first side and a second side, the wafer comprising a plurality of image sensors;

coupling the first side of the wafer to an optically transmissive layer forming a plurality of cavities between the first side of the wafer and the optically transmissive layer;

coupling a redistribution layer (RDL) to the second side of the wafer;

forming a plurality of notches between each image sensor of the plurality of image sensors, the plurality of notches each extending through a thickness of the wafer into the optically transmissive layer;

filling the plurality of notches with a liquid mold material; and

singulating each image sensor of the plurality of image sensors at each notch of the plurality of notches to form a plurality of chip scale packages.

2. The method of claim 1 , further comprising encapsulating a portion of the RDL with the liquid mold material.

3. The method of claim 1 , wherein forming a plurality of cavities between the first side of the wafer and the optically transmissive layer comprises using a plurality of cavity walls.

4. The method of claim 1 , wherein filling the plurality of notches with a liquid mold material further comprises using vacuum.

5. A method of forming a chip scale package, the method comprising:

providing a wafer comprising a first side and a second side, the wafer comprising a plurality of image sensors;

coupling the first side of the wafer to an optically transmissive layer forming a plurality of cavities between the first side of the wafer and the optically transmissive layer;

coupling a redistribution layer (RDL) to the second side of the wafer;

forming a plurality of notches between each image sensor of the plurality of image sensors, the plurality of notches each extending through a thickness of the wafer into the optically transmissive layer;

filling the plurality of notches with a solid mold material; and

singulating each image sensor of the plurality of image sensors at each notch of the plurality of notches to form a plurality of chip scale packages.

6. The method of claim 5 , further comprising encapsulating a portion of the RDL with the solid mold material.

7. The method of claim 5 , wherein forming a plurality of cavities between the first side of the wafer and the optically transmissive layer comprises using a plurality of cavity walls.

8. The method of claim 5 , wherein filling the plurality of notches with a solid mold material further comprises using vacuum.

9. The method of claim 5 , wherein filling the plurality of notches with a solid mold compound further comprises using heat and pressure.

10. A chip scale package comprising:

an image sensor comprising a first side and a second side;

a first cavity wall and a second cavity wall coupled to the first side of the image sensor and to an optically transmissive layer, wherein the first cavity wall and the second cavity wall and the optically transmissive layer form a cavity over the image sensor;

a redistribution layer (RDL) coupled to the second side of the image sensor; and

a mold material, wherein the mold material extends along a portion of the RDL, an angled portion of the image sensor, a side of each cavity wall, and a portion of the optically transmissive layer.

11. The package of claim 10 , wherein the mold material forms a layer parallel with the image sensor and extends along a portion of the RDL, a side of each cavity wall, and a portion of the transparent layer in a direction perpendicular to the image sensor.

12. The package of claim 10 , wherein the mold material is one of a solid mold material or a liquid mold material.

13. The package of claim 10 , further comprising at least one interconnect coupled with the RDL wherein the interconnect is one of a solder ball, a pillar, a copper ball, a gold ball, and any combination thereof.

14. The package of claim 10 , wherein the mold material is a laminatable molding material.

15. The package of claim 10 , wherein the angled portion of the image sensor extends fully across a thickness of the image sensor.

16. The package of claim 10 , wherein the angled portion of the image sensor extends partially across a thickness of the image sensor.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL 056595, FRAME 0177 Recorded Aug 16, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 064615/0564 →
SECURITY INTEREST Recorded Jun 15, 2021
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 056595/0177 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 29, 2021
From: WU, WENG-JIN
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 055075/0697 →