IP Library Granted Patent US 11,145,579
Granted Patent B1
US 11,145,579 · App. 17/169,304 · Granted Oct 12, 2021

Thermally enhanced electronic packages for GaN power integrated circuits

Inventors: Daniel M. Kinzer (El Segundo, CA); Jason Zhang (Monterey Park, CA); Thomas Ribarich (Laguna Beach, CA)
Assignee: Navitas Semiconductor Limited
H01L23/49575H01L24/48H01L24/73H01L25/16H01L2224/48245H01L2224/73265H01L2924/1033H01L2924/1425
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Quick Facts
Patent No.
US 11,145,579
App. No.
17/169,304
Granted
Oct 12, 2021
Kind
B1
Abstract

An electronic power conversion component includes an electrically conductive package base comprising a source terminal, a drain terminal, at least one I/O terminal and a die-attach pad wherein the source terminal is electrically isolated from the die-attach pad. A GaN-based semiconductor die is secured to the die attach pad and includes a power transistor having a source and a drain, wherein the source is electrically coupled to the source terminal and the drain is electrically coupled to the drain terminal. A plurality of wirebonds electrically couple the source to the source terminal and the drain to the drain terminal. An encapsulant is formed over the GaN-based semiconductor die, the plurality of wirebonds and at least a top surface of the package base.

Claims (23)

1. An electronic device comprising:

a leadframe including a die-attach pad, a drain terminal, a source terminal and at least one I/O terminal, wherein the die-attach pad, the drain terminal, the source terminal and the at least one I/O terminal are electrically isolated from each other; and

a gallium nitride (GaN) based device having a substrate electrically connected to the die-attach pad and including a drain coupled to the drain terminal, a source coupled to the source terminal and an I/O coupled to the at least one I/O terminal, wherein the substrate is electrically connected to a ground through the die-attach pad.

2. The electronic device of claim 1 wherein the GaN-based device includes a power field-effect transistor (FET) and a pull-down transistor that is coupled to the power FET.

3. The electronic device of claim 1 wherein the GaN-based device includes at least a portion of a driver circuit for the GaN-based device.

4. The electronic device of claim 1 wherein one of the at least one I/O terminals includes a digital input coupled to a driver circuit for controlling operation of the GaN-based device.

5. The electronic device of claim 1 wherein one of the at least one I/O terminals includes a ratioed output signal that supplies a current that is a fixed ratio of a current flowing through the GaN-based device.

6. The electronic device of claim 5 wherein the ratioed output signal is generated by a silicon-based device that is co-packaged with the GaN-based device.

7. The electronic device of claim 5 wherein the at least one I/O terminal is configured to be coupled to a first terminal of an external current sense resistor, and wherein the die attach pad is configured to be coupled to a second terminal of the current sense resistor.

8. The electronic device of claim 1 wherein the drain terminal is separated from the die attach pad by a spacing of at least 1 millimeter.

9. The electronic device of claim 1 further comprising a silicon-based device attached to the die attach pad and coupled to the GaN-based device.

10. The electronic device of claim 1 further comprising a silicon-based device that is stacked on top of and electrically coupled to the GaN-based device.

11. The electronic device of claim 1 further comprising a Zener diode device that is co-packaged with the GaN-based device.

12. The electronic device of claim 11 wherein a breakdown voltage of the Zener diode device is used as a reference for a voltage regulator circuit of the electronic device.

13. An electronic power conversion component comprising:

an electrically conductive package base comprising a source terminal, a drain terminal, at least one I/O terminal and a die-attach pad wherein the source terminal is electrically isolated from the die attach pad;

a GaN-based semiconductor die having a substrate electrically connected to the die attach pad and including a power transistor having a source and a drain, wherein the source is electrically coupled to the source terminal, the drain is electrically coupled to the drain terminal and the substrate is electrically coupled to a ground through the die attach pad;

one or more first wirebonds electrically coupling the source to the source terminal and one or more second wirebonds electrically coupling the drain to the drain terminal; and

an encapsulant formed over the GaN-based semiconductor die and at least a top surface of the package base.

14. The component of claim 13 further comprising a silicon-based device attached to and coupled to the GaN-based semiconductor die.

15. The component of claim 13 wherein one of the least one I/O terminals includes a digital input coupled to a driver circuit for controlling operation of the GaN-based semiconductor die.

16. The component of claim 13 wherein one of the at least one I/O terminals includes a ratioed output signal that supplies a current that is a fixed ratio of a current flowing through the GaN-based semiconductor die.

17. The component of claim 13 further comprising a Zener diode device that is co-packaged with the GaN-based semiconductor die.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 5, 2021
From: KINZER, DANIEL M.; ZHANG, JASON; RIBARICH, THOMAS
To: NAVITAS SEMICONDUCTOR LIMITED
Reel/Frame 055169/0425 →
Continuity (1)
Provisional Application 63077526 · Sep 11, 2020
Cited By (5)
US 12,334,421 US 12,395,093 US 12,713,944 US 12,727,516 US 12,740,440