IP Library › Granted Patent US 11,257,853
Granted Patent B2
US 11,257,853 · App. 17/169,602 · Granted Feb 22, 2022

Semiconductor device

Inventor: Atsushi Umezaki (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L27/1255G09G3/14G09G3/32G09G3/36G11C19/00H01L29/7869H03B1/00H03K3/00H03K17/6871G09G2300/0426G09G2310/0286G09G2330/021
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Quick Facts
Patent No.
US 11,257,853
App. No.
17/169,602
Granted
Feb 22, 2022
Kind
B2
Abstract

Provided is a semiconductor device exemplified by an inverter circuit and a shift register circuit, which is characterized by a reduced number of transistors. The semiconductor device includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to a first wiring, and the other thereof is electrically connected to a second wiring. One of a source and a drain of the second transistor is electrically connected to the first wiring, a gate of the second transistor is electrically connected to a gate of the first transistor, and the other of the source and the drain of the second transistor is electrically connected to one electrode of the capacitor, while the other electrode of the capacitor is electrically connected to a third wiring. The first and second transistors have the same conductivity type.

Claims (79)

1. A semiconductor device comprising:

a shift register circuit comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor;

a sixth transistor;

a seventh transistor; and

a capacitor,

wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor comprises a gate, a first terminal and a second terminal,

wherein the first terminal of the first transistor is electrically connected to the first terminal of the second transistor,

wherein the first terminal of the third transistor is electrically connected to the gate of the first transistor,

wherein the first terminal of the fourth transistor is electrically connected to the gate of the first transistor,

wherein the second terminal of the fourth transistor is electrically connected to the second terminal of the second transistor,

wherein the first terminal of the fifth transistor is electrically connected to the gate of the second transistor,

wherein the second terminal of the fifth transistor is electrically connected to the second terminal of the second transistor,

wherein the gate of the fifth transistor is electrically connected to the gate of the first transistor,

wherein the first terminal of the sixth transistor is electrically connected to the gate of the seventh transistor,

wherein the gate of the sixth transistor is electrically connected to the gate of the first transistor,

wherein the first terminal of the seventh transistor is electrically connected to the gate of the second transistor,

wherein the first terminal of the third transistor is electrically connected to a first electrode of the capacitor, and

wherein the second terminal of the seventh transistor is electrically connected to a second electrode of the capacitor.

2. The semiconductor device according to claim 1 ,

wherein the first to seventh transistors have the same conductivity type.

3. The semiconductor device according to claim 1 ,

wherein at least one of the first to seventh transistors comprises an oxide semiconductor in a channel formation region.

4. A semiconductor device comprising:

a shift register circuit comprising a first flip-flop circuit and a second flip-flop circuit,

wherein the first flip-flop circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and a capacitor,

wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor comprises a gate, a first terminal and a second terminal,

wherein the first terminal of the first transistor is electrically connected to the first terminal of the second transistor,

wherein the first terminal of the third transistor is electrically connected to the gate of the first transistor,

wherein the first terminal of the fourth transistor is electrically connected to the gate of the first transistor,

wherein the second terminal of the fourth transistor is electrically connected to the second terminal of the second transistor,

wherein the first terminal of the fifth transistor is electrically connected to the gate of the second transistor,

wherein the second terminal of the fifth transistor is electrically connected to the second terminal of the second transistor,

wherein the gate of the fifth transistor is electrically connected to the gate of the first transistor,

wherein the first terminal of the sixth transistor is electrically connected to the gate of the seventh transistor,

wherein the gate of the sixth transistor is electrically connected to the gate of the first transistor,

wherein the first terminal of the seventh transistor is electrically connected to the gate of the second transistor,

wherein the first terminal of the third transistor is electrically connected to a first electrode of the capacitor,

wherein the second terminal of the seventh transistor is electrically connected to a second electrode of the capacitor,

wherein the first terminal of the first transistor is electrically connected to an output terminal of the first flip-flop circuit, and

wherein the first terminal of the first transistor is electrically connected to an input terminal of the second flip-flop circuit.

5. The semiconductor device according to claim 4 ,

wherein the first to seventh transistors have the same conductivity type.

6. The semiconductor device according to claim 4 ,

wherein at least one of the first to seventh transistors comprises an oxide semiconductor in a channel formation region.

7. A semiconductor device comprising:

a shift register circuit comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor;

a sixth transistor;

a seventh transistor; and

a capacitor,

wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor comprises a gate, a first terminal and a second terminal,

wherein the first terminal of the first transistor is electrically connected to the first terminal of the second transistor,

wherein the first terminal of the third transistor is electrically connected to the gate of the first transistor,

wherein the first terminal of the fourth transistor is electrically connected to the gate of the first transistor,

wherein the second terminal of the fourth transistor is electrically connected to the second terminal of the second transistor,

wherein the first terminal of the fifth transistor is electrically connected to the gate of the second transistor,

wherein the second terminal of the fifth transistor is electrically connected to the second terminal of the second transistor,

wherein the gate of the fifth transistor is electrically connected to the gate of the first transistor,

wherein the first terminal of the sixth transistor is electrically connected to the gate of the seventh transistor,

wherein the first terminal of the seventh transistor is electrically connected to the gate of the second transistor,

wherein the first terminal of the third transistor is electrically connected to a first electrode of the capacitor, and

wherein the second terminal of the seventh transistor is electrically connected to a second electrode of the capacitor.

8. The semiconductor device according to claim 7 ,

wherein the first to seventh transistors have the same conductivity type.

9. The semiconductor device according to claim 7 ,

wherein at least one of the first to seventh transistors comprises an oxide semiconductor in a channel formation region.

10. The semiconductor device according to claim 7 , further comprising an eighth transistor and a ninth transistor,

wherein each of the eighth transistor and the ninth transistor comprises a gate, a first terminal and a second terminal,

wherein the gate of the eighth transistor is electrically connected to the gate of the sixth transistor, and

wherein the gate of the ninth transistor is electrically connected to the gate of the seventh transistor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 8, 2021
From: UMEZAKI, ATSUSHI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 055175/0975 →
Priority Claims (1)
JP 2011-217150 · Sep 30, 2011 · national
Continuity (8)
Continuation 16699863 · Dec 2, 2019
Continuation 16417864 · May 21, 2019
Continuation 15795321 · Oct 27, 2017
Continuation 15247995 · Aug 26, 2016
Continuation 14594256 · Jan 12, 2015
Continuation 14222822 · Mar 24, 2014
Continuation 13606440 · Sep 7, 2012
Related Publication 20210167099A1 · Jun 3, 2021
Cited By (1)
US 12,211,569