NVMe-MI over SMBus multi-master controller with other SMBus and I2C masters in a single FPGA chip

1. A method for conducting bus arbitration in a hardware tester system comprising a single master controller and a multi-master controller, the method comprising:

configuring the single master controller with arbitration logic operable to communicate on a bus in the hardware tester system using a same arbitration scheme as the multi-master controller, wherein the single master controller and the multi-master controller are coupled to the bus, and wherein the single master controller communicates with an I2C device, and wherein the multi-master controller communicates with a NVMe-MI (NVMe Management Interface) device; and

responsive to a determination by the arbitration logic that the multi-master controller controls the bus, withdrawing the single master controller from attempting to control the bus and following a pre-programmed duration, the arbitration logic invoking a retry mechanism to attempt to control the bus again.

2. The method of claim 1 , further comprising:

responsive to a determination that the multi-master has relinquished control over the bus, the arbitration logic taking control of the bus to enable the single master controller to communicate on the bus.

3. The method of claim 1 , wherein the single master controller and the multi-master controller comprise an I2C/System Management Bus (SMBus) controller.

4. The method of claim 1 , wherein the arbitration logic enables fair-sharing between the single master controller and the multi-master controller.

5. The method of claim 1 , wherein the single master controller and the multi-master controller are integrated within a single FPGA chip.

6. The method of claim 1 , wherein the determination by the arbitration logic that the multi-master controller controls the bus is performed by determining if the multi-master controller is attempting to write ‘0’s on the bus.

7. The method of claim 1 , wherein the single master controller comprises a I2C/SMBus single master controller, wherein the multi-master controller comprises a I2C/SMBus muti-master controller, and wherein the bus comprises an I2C/SMBus interface.

8. The method of claim 7 , wherein the bus comprises a layered architecture operable to enable an NVMe-MI (NVMe Management Interface) device to communicate over the I2C/SMBus interface.

9. The method of claim 1 , wherein the bus comprises a clock signal and a data signal.

10. An apparatus comprising:

a single master controller comprising an arbiter;

an I2C device;

a NVMe-MI (NVMe Management Interface) device;

a bus; and

a multi-master controller communicatively coupled to the single master controller over the bus, wherein the single master controller communicates with the I2C device, and wherein the multi-master controller communicates with the NVMe-MI (NVMe Management Interface) device, and wherein the arbiter is operable to:

communicate on the bus using a same arbitration procedure as the multi-master controller; and

responsive to a determination by the arbiter that the multi-master controller controls the bus, the arbiter is configured to withdraw the single master controller from attempting to control the bus and following a pre-programmed duration, the arbiter is further configured to invoke a retry mechanism to attempt to control the bus again.

11. The apparatus of claim 10 , wherein the multi-master controller comprises a I2C/SMBus muti-master controller, and wherein the single master controller comprises a I2C/SMBus single master controller.

12. The apparatus of claim 10 , wherein the single master controller and the multi-master controller are integrated within an FPGA chip, wherein the arbiter is transparent to the single master controller, and wherein the arbiter is further transparent to other modules in the FPGA chip.

13. The apparatus of claim 10 , wherein the single master controller and the multi-master controller are integrated within a single FPGA chip.

14. A system comprising:

a single master controller comprising arbitration logic;

a bus; and

a plurality of multi-master controllers communicatively coupled to the single master controller over the bus, wherein the single master controller communicates with an I2C device, and wherein at least one of multi-master controllers communicates with a NVMe-MI (NVMe Management Interface) device, and wherein the arbitration logic is operable to communicate on the bus using a same arbitration scheme as the plurality of multi-master controllers, and wherein further responsive to a determination by the arbitration logic that a multi-master controller of the plurality of multi-master controllers controls the bus, the arbitration logic is configured to withdraw the single master controller from attempting to control the bus, and wherein following a pre-programmed time duration, the arbitration logic is further configured to attempt to control the bus using a retry mechanism to allow the single master controller to communicate on the bus.

15. The system of claim 14 , wherein the single master controller comprises a I2C/SMBus single master controller, wherein the multi-master controller comprises a I2C/SMBus muti-master controller, and wherein the bus comprises an I2C/SMBus interface.

16. The system of claim 14 , wherein responsive to a determination that the multi-master has relinquished control over the bus, the arbitration logic is further configured to take control of the bus to allow the single master controller to communicate on the bus.