Backpower-safe test switch
Disclosed embodiments provide backpower-safe test switches, devices, systems, and methods. By maintaining high impedance on an existing communications bus integrated circuit pin, disclosed embodiments prevent backpower of integrated circuits even when the integrated circuits are powered off. In a non-limiting aspect, disclosed embodiments facilitate increased final ASIC test coverage by facilitating multiplexing analog test bus on an existing ASIC pin.
1 . An apparatus comprising:
an application specific integrated circuit (ASIC) configured to interface with a communications bus via a pin of a package comprising the ASIC according to a communications protocol;
a first switching means for maintaining a high impedance at the pin when the ASIC is powered off, wherein the first switching means comprises a p-channel metal-oxide-semiconductor (PMOS) transistor coupled between the pin connected to the communications bus and a gate of a PMOS transmission transistor in a back to back transmission gate, and wherein the PMOS transistor is configured to maintain the PMOS transmission transistor off as a voltage level applied to the pin is held at a high level according to the communications protocol; and
a second switching means for enabling communications via the communications bus at the pin when the ASIC is powered on.
2 . The apparatus of claim 1 , wherein the communications bus comprises an open drain communications bus.
3 . The apparatus of claim 2 , wherein the open drain communications bus comprises an Inter-Integrated Circuit (I 2 C) bus or wherein the communications protocol is an implementation based at least in part on I 2 C communications protocols.
4 . The apparatus of claim 1 , further comprising:
at least one microelectromechanical systems (MEMS) sensor in the package comprising at least one of an acoustic sensor, a pressure sensor, a temperature sensor, an accelerometer, a vibratory rate gyroscopic sensor, or an environmental sensor.
5 . The apparatus of claim 1 , wherein the second switching means comprises a n-channel metal-oxide-semiconductor (NMOS) transistor coupled between the PMOS transistor and ground, and wherein the NMOS transistor is configured to turn the PMOS transmission transistor on according an enable signal from the ASIC when the ASIC is powered on.
6 . The apparatus of claim 1 , wherein the ASIC is configured to accept a multiplexed analog test signal on the pin without backpowering the ASIC by maintaining the high impedance at the pin when the ASIC is powered off.
7 . An apparatus, comprising:
a package comprising an application specific integrated circuit (ASIC), wherein the ASIC is configured to interface with a communications bus via a pin of the package according to a communications protocol;
a p-channel metal-oxide-semiconductor (PMOS) transistor coupled between the pin and a gate of a PMOS transmission transistor in a back to back transmission gate, wherein the PMOS transistor is configured to maintain the PMOS transmission transistor off, with the ASIC powered off, as a voltage level applied to the pin is held at a high level according to the communications protocol; and
a n-channel metal-oxide-semiconductor (NMOS) transistor coupled between the PMOS transistor and ground, and wherein the NMOS transistor is configured to turn the PMOS transmission transistor on according an enable signal from the ASIC when the ASIC is powered on.
8 . The apparatus of claim 7 , wherein the PMOS transistor is configured to apply the voltage level applied to the pin at the high level to a gate of the PMOS transmission transistor to maintain the PMOS transmission transistor off and to block the voltage level applied to the pin at the high level when the ASIC is powered off.
9 . The apparatus of claim 8 , wherein the NMOS transistor is configured to short the gate of the PMOS transmission transistor to ground to maintain the PMOS transmission transistor on and to pass the voltage level applied to the pin at the high level when the ASIC is powered on.
10 . The apparatus of claim 7 , wherein the communications bus comprises an open drain communications bus.
11 . The apparatus of claim 7 , wherein a device comprising the ASIC is multiplexed on an I 2 C bus with at least one other device configured to communicate based at least in part on I 2 C protocols and is configured to be exposed to the voltage level applied to the pin at the high level.
12 . The apparatus of claim 7 , further configured to accept a multiplexed analog test signal on the pin without backpowering the ASIC by maintaining a high impedance at the pin when the ASIC is powered off.
13 . An apparatus comprising:
an application specific integrated circuit (ASIC) communicatively coupled to at least one microelectromechanical systems (MEMS) sensor and configured to process at least one signal from the at least one MEMS sensor;
a package comprising the at least one MEMS sensor and the ASIC;
a pin of the package coupled between the ASIC and a communications bus according to a communications protocol;
a backpower-safe switch coupled between the ASIC and the pin, wherein the backpower-safe switch is configured to provide a high impedance at the pin when the ASIC is powered off, wherein the backpower-safe switch is further configured to enable communications with the communications bus according to the communications protocol when the ASIC is powered on, wherein the backpower-safe switch comprises a first switching means for maintaining the high impedance at the pin when the ASIC is powered off, and wherein the first switching means comprises a p-channel metal-oxide-semiconductor (PMOS) transistor coupled between the pin coupled to the communications bus and a gate of a PMOS transmission transistor in a back to back transmission gate, and wherein the PMOS transistor is configured to maintain the PMOS transmission transistor off as a voltage level applied to the pin is held at a high level according to the communications protocol.
14 . The apparatus of claim 13 , wherein the backpower-safe switch comprises a second switching means for enabling the communications via the communications bus at the pin when the ASIC is powered on.
15 . The apparatus of claim 14 , wherein the second switching means comprises a n-channel metal-oxide-semiconductor (NMOS) transistor coupled between the PMOS transistor and ground, and wherein the NMOS transistor is configured to turn the PMOS transmission transistor on according an enable signal from the ASIC when the ASIC is powered on.
16 . The apparatus of claim 13 , wherein the communications bus comprises an open drain communications bus.
17 . The apparatus of claim 16 , wherein the open drain communications bus comprises an Inter-Integrated Circuit (I 2 C) bus or wherein the communications protocol is an implementation based at least in part on I 2 C communications protocols.
18 . The apparatus of claim 13 , wherein the backpower-safe switch is further configured to accept a multiplexed analog test signal on the pin without backpowering the ASIC by maintaining the high impedance at the pin when the ASIC is powered off.