Supply voltage detection circuit
A supply voltage detection circuit determines when the voltage for any one of the power supply signals received by an integrated circuit device is below its steady state level, as may occur during a hot socket condition when the device is inserted in or removed from a powered-on system. A first detection circuit determines when the first supply voltage level is below its steady state level, and a second detection circuit determines when the second supply voltage level is below its steady state level. A logic circuit provides a detected condition signal that disables current flow through an input/output terminal associated with the supply voltage detection circuit. The circuit is able to rapidly detect hot socket conditions for a wide range of power supply signal levels, including low supply signal levels, while limiting leakage current effects.
1. A voltage detection circuit comprising:
a first latch having an input and an output, an output of said voltage detection circuit being at the input of the first latch;
a first transistor coupled between an input of said voltage detection circuit and the output of the first latch, the first transistor having a control terminal coupled to a node for a power signal for said voltage detection circuit; and
a second transistor coupled between a reference supply voltage and the input of the first latch, the second transistor having a control terminal coupled to the input of said voltage detection circuit.
2. The detection circuit of claim 1 wherein the first transistor has a lower conductivity than the second transistor.
3. The detection circuit of claim 1 wherein
the first transistor is an NMOS transistor having a source terminal coupled to the input of said voltage detection circuit, a drain terminal coupled to the output of the first latch, and a gate terminal coupled to the power signal node for said voltage detection circuit; and
the second transistor is an NMOS transistor having a source terminal coupled to the reference supply voltage, a drain terminal coupled to the input of the first latch, and a gate terminal coupled to the input of said voltage detection circuit.
4. The detection circuit of claim 1 wherein the first latch is a half latch comprising:
an inverter having an input and an output, the input of the inverter being the input of the first latch and the output of the inverter being the output of the first latch; and
a third transistor coupled between the input of the first latch and the power signal node for said voltage detection circuit, the third transistor having a control terminal coupled to the output of the first latch.
5. The detection circuit of claim 4 further comprising detection circuits includes a second half latch comprising:
a second inverter having an input and an output, the input of the second inverter being coupled to the input of the first latch;
a fourth transistor coupled between the input of the first latch and the power signal node for said voltage detection circuit, the third transistor having a control terminal coupled to the output of the second inverter.
6. The detection circuit of claim 5 wherein
the third transistor is a PMOS transistor having a source terminal coupled to the power signal node for said voltage detection circuit, a drain terminal coupled to the input of the first latch, and a gate terminal coupled to the output of the first latch; and
the fourth transistor is a PMOS transistor having a source terminal coupled to the power signal node for said voltage detection circuit, a drain terminal coupled to the input of the first latch, and a gate terminal coupled to the output of the second inverter.
7. A supply voltage detection circuit for an input/output terminal of an integrated circuit device, comprising:
a first voltage detection circuit having an input for receiving a first supply voltage signal and an output for providing a first detection signal that indicates when the voltage level of the first supply voltage signal is below a first steady state supply level;
a second voltage detection circuit having an input for receiving a second supply voltage signal and an output for providing a second detection signal that indicates when the voltage level of the second supply voltage signal is below a second steady state supply level; and
a logic circuit for receiving the first and second detection signals and providing at least one detected condition signal for disabling current flow through the input/output terminal when either the first supply voltage signal is below the first steady state supply level or the second supply voltage signal is below the second steady state supply level,
wherein the first steady state supply level is greater than or equal to the second steady state supply level, the power signal for the first voltage detection circuit is the greater of the first supply voltage signal and a signal corresponding to the voltage at the input/output terminal, and the power signal for the second voltage detection circuit is the first supply voltage signal.
8. The detection circuit of claim 7 wherein the first steady state supply level is greater than or equal to the second steady state supply level, and the power signal for each of the first and second voltage detection circuits is the greater of the first supply voltage signal and a signal corresponding to the voltage at the input/output terminal.
9. The detection circuit of claim 7 wherein each of the first and second voltage detection circuits comprises:
a first latch having an input and an output, the output of said voltage detection circuit being at the input of the first latch;
a first transistor coupled between the input of said voltage detection circuit and the output of the first latch, the first transistor having a control terminal coupled to a node for a power signal for said voltage detection circuit; and
a second transistor coupled between a reference supply voltage and the input of the first latch, the second transistor having a control terminal coupled to the input of said voltage detection circuit.
10. The detection circuit of claim 9 wherein the first transistor has a lower conductivity than the second transistor.
11. The detection circuit of claim 9 wherein
the first transistor is an NMOS transistor having a source terminal coupled to the input of said voltage detection circuit, a drain terminal coupled to the output of the first latch, and a gate terminal coupled to the power signal node for said voltage detection circuit; and
the second transistor is an NMOS transistor having a source terminal coupled to the reference supply voltage, a drain terminal coupled to the input of the first latch, and a gate terminal coupled to the input of said voltage detection circuit.
12. The detection circuit of claim 9 wherein the first latch is a half latch comprising:
an inverter having an input and an output, the input of the inverter being the input of the first latch and the output of the inverter being the output of the first latch; and
a third transistor coupled between the input of the first latch and the power signal node for said voltage detection circuit, the third transistor having a control terminal coupled to the output of the first latch.
13. The detection circuit of claim 12 wherein each of the first and second voltage detection circuits includes a second half latch comprising:
a second inverter having an input and an output, the input of the second inverter being coupled to the input of the first latch;
a fourth transistor coupled between the input of the first latch and the power signal node for said voltage detection circuit, the third transistor having a control terminal coupled to the output of the second inverter.
14. The detection circuit of claim 13 wherein
the third transistor is a PMOS transistor having a source terminal coupled to the power signal node for said voltage detection circuit, a drain terminal coupled to the input of the first latch, and a gate terminal coupled to the output of the first latch; and
the fourth transistor is a PMOS transistor having a source terminal coupled to the power signal node for said voltage detection circuit, a drain terminal coupled to the input of the first latch, and a gate terminal coupled to the output of the second inverter.