IP Library Granted Patent US 11,219,123
Granted Patent B2
US 11,219,123 · App. 17/173,102 · Granted Jan 4, 2022

Printed circuit board and method for manufacturing same

Inventors: Fumihiko Matsuda (Tokyo, JP); Yoshihiko Narisawa (Tokyo, JP); Kenji Kumagai (Tokyo, JP); Daisuke Shiokawa (Tokyo, JP); Yuki Ogi (Tokyo, JP); Akihiko Toyoshima (Tokyo, JP); Masami Uchino (Tokyo, JP); Isao Arase (Tokyo, JP); Hiroshi Takeuchi (Tokyo, JP)
Assignee: NIPPON MEKTRON, LTD.
H05K1/0296H05K1/0284H05K1/032H05K2201/0141
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Quick Facts
Patent No.
US 11,219,123
App. No.
17/173,102
Granted
Jan 4, 2022
Kind
B2
Abstract

Provided is a printed circuit board which includes: a first dielectric layer including a first principal surface and a second principal surface on a side opposite to the first principal surface; a first adhesive layer formed on the first principal surface; a first metal foil pattern formed on the first adhesive layer and forming a signal line; and a second metal foil pattern formed on the second principal surface and forming a ground layer, in which the first metal foil pattern has a higher specific conductivity than a specific conductivity of the second metal foil pattern.

Claims (48)

1. A printed circuit board comprising:

a first dielectric layer including a first principal surface and a second principal surface on a side opposite to the first principal surface;

a first adhesive layer formed on the first principal surface;

a first metal foil pattern formed on the first adhesive layer and forming a signal line; and

a second metal foil pattern formed on the second principal surface and forming a ground layer,

wherein the first metal foil pattern has a higher specific conductivity than a specific conductivity of the second metal foil pattern.

2. The printed circuit board according to claim 1 , wherein

the first dielectric layer is made of liquid crystal polymer.

3. The printed circuit board according to claim 1 , further comprising:

a second dielectric layer including a third principal surface and a fourth principal surface on a side opposite to the third principal surface;

a second adhesive layer formed on the fourth principal surface and bonded to the first adhesive layer; and

a third metal foil pattern formed on the third principal surface and forming a ground layer,

wherein the first metal foil pattern has a higher specific conductivity than a specific conductivity of the third metal foil pattern.

4. The printed circuit board according to claim 3 , wherein

the second adhesive layer is thicker than the first metal foil pattern, and

the first metal foil pattern is embedded in an adhesive layer including the first adhesive layer and the second adhesive layer.

5. The printed circuit board according to claim 4 , wherein

the first dielectric layer and the second dielectric layer have an identical thickness, and

the first adhesive layer and the second adhesive layer have an identical thickness.

6. The printed circuit board according to claim 4 , wherein

the first dielectric layer and the second dielectric layer have an identical thickness, and

the first adhesive layer is thinner than the second adhesive layer by a thickness of the first metal foil pattern.

7. The printed circuit board according to claim 3 , wherein

the second dielectric layer is made of liquid crystal polymer.

8. The printed circuit board according to claim 3 , wherein

the first metal foil pattern has a lower surface roughness and/or contains a smaller magnetic metal amount than those of the second metal foil pattern and the third metal foil pattern.

9. The printed circuit board according to claim 8 , wherein

a ten-point average roughness of the first metal foil pattern is equal to or lower than 1.0 μm.

10. The printed circuit board according to claim 3 , further comprising:

a fourth metal foil pattern formed on the first adhesive layer, extending in parallel with the signal line of the first metal foil pattern with a predetermined spacing from the signal line of the first metal foil pattern, and forming a ground wire;

a first ground connection portion electrically connecting the second metal foil pattern and the fourth metal foil pattern; and

a second ground connection portion electrically connecting the third metal foil pattern and the fourth metal foil pattern.

11. The printed circuit board according to claim 10 , wherein

the first ground connection portion includes a through-hole penetrating the first dielectric layer in a thickness direction and filled with hardened conductive paste, and

the second ground connection portion includes a through-hole penetrating the second dielectric layer in the thickness direction and filled with hardened conductive paste.

12. The printed circuit board according to claim 10 , wherein

the first ground connection portion includes a metal plating layer formed in a through-hole penetrating the first dielectric layer in a thickness direction, and

the second ground connection portion includes a metal plating layer formed in a through-hole penetrating the second dielectric layer in the thickness direction.

13. A printed circuit board comprising:

a first dielectric layer including a first principal surface and a second principal surface on a side opposite to the first principal surface;

a first adhesive layer formed on the first principal surface;

a first metal foil pattern formed on the first adhesive layer and forming a signal line;

a second metal foil pattern formed on the second principal surface and forming a ground layer;

a second dielectric layer including a third principal surface and a fourth principal surface on a side opposite to the third principal surface;

a second adhesive layer formed on the fourth principal surface and bonded to the first adhesive layer; and

a third metal foil pattern formed on the third principal surface and forming a ground layer,

wherein the second adhesive layer is thicker than the first metal foil pattern, and

the first metal foil pattern is embedded in an adhesive layer including the first adhesive layer and the second adhesive layer.

Assignments (2)
CHANGE OF NAME Recorded Nov 30, 2024
From: NIPPON MEKTRON, LTD.
To: MEKTEC CORPORATION
Reel/Frame 069464/0771 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 10, 2021
From: MATSUDA, FUMIHIKO; NARISAWA, YOSHIHIKO; KUMAGAI, KENJI; SHIOKAWA, DAISUKE; OGI, YUKI; TOYOSHIMA, AKIHIKO; UCHINO, MASAMI; ARASE, ISAO; TAKEUCHI, HIROSHI
To: NIPPON MEKTRON, LTD.
Reel/Frame 055220/0497 →
Priority Claims (1)
JP JP2020-037868 · Mar 5, 2020 · national
Continuity (1)
Related Publication 20210282263A1 · Sep 9, 2021