Integrated circuit package and method
In an embodiment, a method includes: bonding a back side of a first memory device to a front side of a second memory device with dielectric-to-dielectric bonds and with metal-to-metal bonds; after the bonding, forming first conductive bumps through a first dielectric layer at a front side of the first memory device, the first conductive bumps raised from a major surface of the first dielectric layer; testing the first memory device and the second memory device using the first conductive bumps; and after the testing, attaching a logic device to the first conductive bumps with reflowable connectors.
1. A method comprising:
bonding a back side of a first memory device to a front side of a second memory device with dielectric-to-dielectric bonds and with metal-to-metal bonds;
after the bonding, forming first conductive bumps through a first dielectric layer at a front side of the first memory device, the first conductive bumps raised from a major surface of the first dielectric layer;
testing the first memory device and the second memory device using the first conductive bumps; and
after the testing, attaching a logic device to the first conductive bumps with reflowable connectors.
2. The method of claim 1 , wherein the bonding the back side of the first memory device to the front side of the second memory device comprises bonding a back side of a first wafer to a front side of a second wafer with dielectric-to-dielectric bonds and with metal-to-metal bonds, the first wafer comprising the first memory device, the second wafer comprising the second memory device, the method further comprising:
after the bonding, singulating the first memory device and the second memory device.
3. The method of claim 1 , wherein the bonding the back side of the first memory device to the front side of the second memory device comprises bonding a back side of a first integrated circuit die to a front side of a second integrated circuit die with dielectric-to-dielectric bonds and with metal-to-metal bonds, the method further comprising:
after the bonding, forming a second dielectric layer around the first integrated circuit die and the second integrated circuit die.
4. The method of claim 1 , wherein the bonding the back side of the first memory device to the front side of the second memory device comprises:
pressing the second memory device against the first memory device; and
annealing the first memory device and the second memory device.
5. The method of claim 1 further comprising:
bonding a front side of a passive device to a back side of the second memory device with dielectric-to-dielectric bonds and with metal-to-metal bonds;
forming a second dielectric layer around the passive device;
forming conductive vias extending through the second dielectric layer; and
bonding a front side of a third memory device to the conductive vias and a back side of the passive device with metal-to-metal bonds, and to the second dielectric layer and the back side of the passive device with dielectric-to-dielectric bonds.
6. The method of claim 1 , wherein the attaching the logic device to the first conductive bumps with the reflowable connectors comprises:
obtaining a wafer comprising the logic device and second conductive bumps, the second conductive bumps disposed at a back side of the wafer; and
soldering the first conductive bumps to the second conductive bumps with the reflowable connectors.
7. The method of claim 1 , wherein the attaching the logic device to the first conductive bumps with the reflowable connectors comprises:
forming a package component comprising the logic device, an encapsulant, and second conductive bumps, the encapsulant surrounding the logic device, the second conductive bumps connected to the logic device; and
soldering the first conductive bumps to the second conductive bumps with the reflowable connectors.
8. The method of claim 1 , wherein the attaching the logic device to the first conductive bumps with the reflowable connectors comprises:
obtaining an integrated circuit die, the integrated circuit die comprising second conductive bumps at a back side of the integrated circuit die; and
soldering the first conductive bumps to the second conductive bumps with the reflowable connectors.
9. The method of claim 1 , wherein the logic device is an interface device for the first memory device and the second memory device, the method further comprising:
attaching the interface device and a processor device to an interposer; and
attaching the interposer to a package substrate.
10. The method of claim 1 , wherein the logic device is an interface device for the first memory device and the second memory device, the method further comprising:
attaching the interface device and a processor device to a wafer-level redistribution structure; and
attaching the wafer-level redistribution structure to a package substrate.
11. The method of claim 1 , wherein the logic device is an interface device for the first memory device and the second memory device, the method further comprising:
forming a first redistribution structure;
forming a conductive via extending from the first redistribution structure;
placing a bridge die adjacent the conductive via;
encapsulating the bridge die and the conductive via with an encapsulant;
forming a second redistribution structure on the encapsulant, the bridge die, and the conductive via;
attaching the interface device and a processor device to the first redistribution structure; and
attaching the second redistribution structure to a package substrate.
12. A method comprising:
stacking a plurality of memory devices over a carrier substrate;
removing the carrier substrate to reveal a major surface of a dielectric layer at a front side of an upper memory device of the memory devices;
after the removing, forming conductive bumps through the dielectric layer, the conductive bumps raised from the major surface of the dielectric layer;
testing each of the memory devices using the conductive bumps; and
after the testing, attaching a logic device to the conductive bumps with reflowable connectors.
13. The method of claim 12 , wherein stacking the memory devices comprises stacking the memory devices with hybrid bonding.
14. The method of claim 12 further comprising:
forming an oxide layer surrounding the memory devices.
15. A method comprising:
bonding a tested memory cube to a logic device with first reflowable connectors, the tested memory cube comprising a plurality of first memory devices back-to-face bonded with dielectric-to-dielectric bonds and with metal-to-metal bonds, a top memory device of the tested memory cube comprising first conductive bumps at a front side of the top memory device, each respective lower memory device of the tested memory cube comprising bond pads at a front side of the respective lower memory device, the logic device comprising second conductive bumps, the first reflowable connectors physically and electrically coupling the first conductive bumps to the second conductive bumps; and
forming a first underfill between the logic device and the tested memory cube, the first underfill surrounding each of the first reflowable connectors.
16. The method of claim 15 further comprising:
encapsulating the first underfill and each of the first memory devices.
17. The method of claim 15 further comprising:
forming a dielectric layer surrounding each of the first memory devices; and
encapsulating the first underfill and the dielectric layer.
18. The method of claim 15 , wherein the tested memory cube further comprises a passive device at an intermediate layer of the tested memory cube.
19. The method of claim 15 , wherein a width of the logic device is greater than a width of the tested memory cube.
20. The method of claim 15 , wherein a width of the logic device is less than a width of the tested memory cube.