Integrated circuit device

1. An integrated circuit device comprising:

a substrate comprising a first fin-type active area and a second fin-type active area;

a gate structure extending in a first direction on the first fin-type active area and the second fin-type active area, the first direction being parallel to an upper surface of the substrate;

a first source/drain region on a side of the gate structure on the first fin-type active area;

a second source/drain region on a side of the gate structure on the second fin-type active area;

a first source/drain contact on the first source/drain region, the first source/drain contact comprising a first portion and a second portion, the second portion of the first source/drain contact having an upper surface that is lower than an upper surface of the first portion of the first source/drain contact relative to the substrate;

a second source/drain contact on the second source/drain region, the second source/drain contact comprising a first portion and a second portion, the second portion of the second source/drain contact having an upper surface that is lower than an upper surface of the first portion of the second source/drain contact relative to the substrate;

a first stressor layer on the upper surface of the second portion of the first source/drain contact; and

a second stressor layer on the upper surface of the second portion of the second source/drain contact, the second stressor layer comprising a second material that is different from a first material of the first stressor layer.

2. The integrated circuit device of claim 1 , wherein the first stressor layer extends on side walls of the first portion of the first source/drain contact, and an upper surface of the first stressor layer is substantially coplanar with the upper surface of the first portion of the first source/drain contact, and

wherein the second stressor layer extends on side walls of the first portion of the second source/drain contact, and an upper surface of the second stressor layer is substantially coplanar with the upper surface of the first portion of the second source/drain contact.

3. The integrated circuit device of claim 1 , wherein, relative to the substrate, the upper surface of the second portion of the first source/drain contact is lower than an upper surface of the gate structure, and a bottom surface of the first stressor layer is lower than the upper surface of the gate structure.

4. The integrated circuit device of claim 1 , wherein, relative to the substrate, the upper surface of the second portion of the second source/drain contact is lower than an upper surface of the gate structure, and a bottom surface of the second stressor layer is lower than the upper surface of the gate structure.

5. The integrated circuit device of claim 1 , further comprising:

a first gate contact on the gate structure on the first fin-type active area, wherein the first stressor layer extends on side walls of the first gate contact; and/or

a second gate contact on the gate structure on the second fin-type active area, wherein the second stressor layer extends on side walls of the second gate contact.

6. The integrated circuit device of claim 5 , wherein, along a direction parallel to the upper surface of the substrate, the first gate contact has a larger separation distance from the first portion of the first source/drain contact than from the second portion of the first source/drain contact, and/or the second gate contact has a larger separation distance from the first portion of the second source/drain contact than from the second portion of the second source/drain contact.

7. The integrated circuit device of claim 1 , wherein an upper surface of the first stressor layer is substantially coplanar with an upper surface of the second stressor layer, and a side wall of the first stressor layer is in contact with a side wall of the second stressor layer.

8. The integrated circuit device of claim 1 , further comprising:

an inter-gate insulating layer on opposing side walls of the gate structure, and between the first source/drain region and the second source/drain region,

wherein the substrate further comprises a deep trench area between the first and second fin-type active areas, and

wherein a side wall of the first stressor layer and a side wall of the second stressor layer are in contact with each other on the inter-gate insulating layer on the deep trench area.

9. The integrated circuit device of claim 1 , further comprising:

a contact liner extending on side walls of the first source/drain contact,

wherein a portion of the contact liner extending on the side walls of the second portion of the first source/drain contact is in contact with the first stressor layer.

10. The integrated circuit device of claim 1 , further comprising:

a gate capping layer on an upper surface of the gate structure and having a convex upper surface having the first stressor layer thereon;

a conductive via on the first portion of the first source/drain contact; and

a wiring layer on the conductive via.

11. The integrated circuit device of claim 1 , wherein the first stressor layer comprises SiOC, SiON, SiCN, SiN, Tonen SilaZene (TOSZ), tetraethyl orthosilicate (TEOS), atomic layer deposition (ALD) oxide, flowable chemical vapor deposition (FCVD) oxide, high density plasma (HDP) oxide, and/or plasma enhanced oxidation (PEOX) oxide, and

wherein the second stressor layer comprises SiOC, SiON, SiCN, SiN, TOSZ, TEOS, ALD oxide, FCVD oxide, HDP oxide, and/or PEOX oxide.

12. An integrated circuit device comprising:

a substrate comprising a first fin-type active area and a second fin-type active area, the first fin-type active area and the second fin-type active area extending in a first direction;

a gate structure extending in a second direction on the first fin-type active area and the second fin-type active area, the second direction being different from the first direction;

a first source/drain region on a side of the gate structure on the first fin-type active area;

a second source/drain region on a side of the gate structure on the second fin-type active area;

a first source/drain contact on the first source/drain region, the first source/drain contact comprising a first portion and a second portion, the second portion of the first source/drain contact having an upper surface that is lower than an upper surface of the first portion of the first source/drain contact relative to the substrate;

a second source/drain contact on the second source/drain region, the second source/drain contact comprising a first portion and a second portion, the second portion of the second source/drain contact having an upper surface that is lower than an upper surface of the first portion of the second source/drain contact relative to the substrate;

a first stressor layer on the upper surface of the second portion of the first source/drain contact and having an upper surface that is substantially coplanar with the upper surface of the first portion of the first source/drain contact; and

a second stressor layer on the upper surface of the second portion of the second source/drain contact and having an upper surface that is substantially coplanar with the upper surface of the first portion of the second source/drain contact, the second stressor layer comprising a second material that is different from a first material of the first stressor layer.

13. The integrated circuit device of claim 12 , wherein the first stressor layer extends on side walls of the first portion of the first source/drain contact, and wherein the second stressor layer extends on side walls of the first portion of the second source/drain contact.

14. The integrated circuit device of claim 12 , wherein, relative to the substrate, the upper surface of the second portion of the first source/drain contact is lower than an upper surface of the gate structure, and a bottom surface of the first stressor layer is lower than the upper surface of the gate structure, and

wherein, relative to the substrate, the upper surface of the second portion of the second source/drain contact is lower than the upper surface of the gate structure, and a bottom surface of the second stressor layer is lower than the upper surface of the gate structure.

15. The integrated circuit device of claim 12 , wherein the upper surface of the first stressor layer is substantially coplanar with the upper surface of the second stressor layer, and

wherein a side wall of the first stressor layer is in contact with a side wall of the second stressor layer.

16. The integrated circuit device of claim 12 , further comprising:

a gate capping layer on an upper surface of the gate structure;

a first gate contact on the gate structure, the first gate contact extending in a first gate contact hole that penetrates through the first stressor layer and the gate capping layer; and

a second gate contact on the gate structure, the second gate contact extending in a second gate contact hole that penetrates through the second stressor layer and the gate capping layer.

17. An integrated circuit device comprising:

a first fin-type active area and a second fin-type active area protruding from a substrate and extending in a first direction;

a plurality of first semiconductor patterns spaced apart from an upper surface of the first fin-type active area, the plurality of first semiconductor patterns each including a respective first channel region;

a plurality of second semiconductor patterns spaced apart from an upper surface of the second fin-type active area, the plurality of second semiconductor patterns each including a respective second channel region;

a gate structure extending on the first fin-type active area and the second fin-type active area in a second direction that is perpendicular to the first direction, the gate structure extending on the plurality of first semiconductor patterns and the plurality of second semiconductor patterns;

a first source/drain region on a side of the gate structure and contacting the plurality of first semiconductor patterns;

a second source/drain region on a side of the gate structure and contacting the plurality of second semiconductor patterns;

a first source/drain contact on the first source/drain region, the first source/drain contact comprising a first portion and a second portion, the second portion of the first source/drain contact having an upper surface that is lower than an upper surface of the first portion of the first source/drain contact relative to the substrate;

a second source/drain contact on the second source/drain region, the second source/drain contact comprising a first portion and a second portion, the second portion of the second source/drain contact having an upper surface that is lower than an upper surface of the first portion of the second source/drain contact relative to the substrate;

a first stressor layer on the upper surface of the second portion of the first source/drain contact; and

a second stressor layer on the upper surface of the second portion of the second source/drain contact, the second stressor layer comprising a second material different from a first material of the first stressor layer.

18. The integrated circuit device of claim 17 , wherein the first stressor layer extends on side walls of the first portion of the first source/drain contact, and the second stressor layer extends on side walls of the first portion of the second source/drain contact.

19. The integrated circuit device of claim 17 , wherein, relative to the substrate, the upper surface of the second portion of the first source/drain contact is lower than an upper surface of the gate structure, and the upper surface of the second portion of the second source/drain contact is lower than the upper surface of the gate structure, and

wherein an upper surface of the first stressor layer is substantially coplanar with an upper surface of the second stressor layer, and a side wall of the first stressor layer is in contact with a side wall of the second stressor layer.

20. The integrated circuit device of claim 17 , further comprising:

a gate capping layer on an upper surface of the gate structure;

a first gate contact on the gate structure, the first gate contact extending in a first gate contact hole that penetrates through the first stressor layer and the gate capping layer; and

a second gate contact on the gate structure, the second gate contact extending in a second gate contact hole that penetrates through the second stressor layer and the gate capping layer.