Semiconductor device and manufacturing method thereof
A device includes a channel layer, a gate structure, a first source/drain epitaxial structure, a second source/drain epitaxial structure, a dummy fin structure, a mask layer, a first source/drain contact, and an isolation plug. The gate structure crosses the channel layer. The first source/drain epitaxial structure and the second source/drain epitaxial structure are on opposite sides of the channel layer. The dummy fin structure is in contact with the first source/drain epitaxial structure. The mask layer is over the dummy fin structure. The first source/drain contact is over and electrically connected to the first source/drain epitaxial structure. The isolation plug is over the mask layer and in contact with the first source/drain contact. The isolation plug is directly over the first source/drain contact and the mask layer.
1 . A method comprising:
forming a fin structure over a substrate, wherein the fin structure comprises first semiconductor layers and second semiconductor layers alternately stacked;
forming a dummy gate structure over the fin structure;
removing a portion of the fin structure uncovered by the dummy gate structure;
growing a source/drain epitaxial structure on a side of remaining portions of the second semiconductor layers;
forming an interlayer dielectric (ILD) layer over the source/drain epitaxial structure and surrounding the dummy gate structure;
replacing the dummy gate structure and the first semiconductor layers with a metal gate structure;
removing the ILD layer to expose the source/drain epitaxial structure;
after removing the ILD layer, forming a conductive layer over the source/drain epitaxial structure;
forming an opening in the conductive layer to cut the conductive layer into a first source/drain contact over the source/drain epitaxial structure and a second source/drain contact, wherein the first source/drain contact is electrically connected to the second source/drain contact prior to forming the opening; and
forming an isolation plug in the opening and between the first source/drain contact and the second source/drain contact, wherein a portion of the first source/drain contact is in contact with a bottom surface of the isolation plug.
2 . The method of claim 1 , further comprising:
forming a dummy fin structure over the substrate; and
forming a mask layer over the dummy fin structure prior to forming the dummy gate structure.
3 . The method of claim 2 , wherein forming the opening in the conductive layer is such that the opening exposes the mask layer.
4 . The method of claim 2 , wherein forming the opening in the conductive layer comprises recessing the mask layer.
5 . The method of claim 2 , further comprising depositing a contact spacer covering the mask layer and the source/drain epitaxial structure prior to forming the conductive layer over the source/drain epitaxial structure.
6 . The method of claim 5 , wherein forming the opening in the conductive layer comprises removing a portion of the contact spacer over the mask layer and another portion of the contact spacer remains on a sidewall of the mask layer.
7 . The method of claim 1 , further comprising forming a contact spacer lining a sidewall of the metal gate structure after removing the ILD layer and prior to forming the conductive layer.
8 . A method comprising:
providing a semiconductor structure comprising:
a substrate; and
a first transistor and a second transistor over the substrate;
removing an interlayer dielectric layer over the first transistor and the second transistor to form a recess exposing a first source/drain epitaxial structure of the first transistor and a second source/drain epitaxial structure of the second transistor;
after removing the interlayer dielectric layer, forming a first metal alloy layer on the first source/drain epitaxial structure;
after removing the interlayer dielectric layer, forming a second metal alloy layer on the second source/drain epitaxial structure;
depositing a conductive layer in the recess, over the first source/drain epitaxial structure and the second source/drain epitaxial structure, and in contact with the first metal alloy layer and the second metal alloy layer;
performing an etching process to the conductive layer to cut the conductive layer into a first source/drain contact connecting the first metal alloy layer and a second source/drain contact connecting the second metal alloy layer;
forming an isolation structure between the first source/drain contact and the second source/drain contact; and
forming a contact spacer lining a sidewall of the recess after removing the interlayer dielectric layer and prior to forming the first metal alloy layer.
9 . The method of claim 8 , wherein the contact spacer further lines an outer surface of the first source/drain epitaxial structure.
10 . The method of claim 8 , wherein a portion of the contact spacer is at a level below the first metal alloy layer.
11 . The method of claim 8 , wherein the etching process is performed to remove a portion of a dielectric cap over a gate structure of the first transistor.
12 . The method of claim 8 , wherein a portion of the first source/drain contact is in contact with a bottom surface of the isolation structure.
13 . The method of claim 8 , wherein the conductive layer extends from the first metal alloy layer to the second metal alloy layer.
14 . A method comprising:
forming a first channel structure and a second channel structure over a substrate;
forming a mask layer between the first channel structure and the second channel structure;
forming a dummy gate structure over the first channel structure, the second channel structure, and the mask layer;
forming a first source/drain epitaxial structure over the substrate and connected to the first channel structure;
forming a second source/drain epitaxial structure over the substrate and connected to the second channel structure;
depositing an interlayer dielectric layer over the first source/drain epitaxial structure, the second source/drain epitaxial structure, and the mask layer;
replacing the dummy gate structure with a metal gate structure;
removing the interlayer dielectric layer;
depositing a conductive layer over the first source/drain epitaxial structure, the second source/drain epitaxial structure, and the mask layer, wherein the conductive layer is in contact with a top surface of the mask layer; and
forming an isolation structure in the conductive layer and in contact with the mask layer.
15 . The method of claim 14 , further comprising forming a contact spacer over the first source/drain epitaxial structure, the second source/drain epitaxial structure, and the mask layer after removing the interlayer dielectric layer and prior to depositing the conductive layer.
16 . The method of claim 15 , wherein the contact spacer is in contact with a sidewall of the mask layer.
17 . The method of claim 14 , wherein the isolation structure is misaligned with the mask layer.
18 . The method of claim 14 , wherein forming the isolation structure comprises:
forming an opening in the conductive layer and exposes the mask layer;
depositing a dielectric material in the opening; and
removing a portion of the dielectric material outside the opening.
19 . The method of claim 18 , wherein forming the opening in the conductive layer comprises etching a top portion of the mask layer.
20 . The method of claim 14 , wherein after forming the isolation structure, a portion of the conductive layer is in contact with a top surface of the mask layer.