Forming single and double diffusion breaks

1. A method of fabricating a semiconductor device, the method comprising:

forming one or more fins on a substrate, the substrate comprising a first region and a second region;

forming a plurality of sacrificial gate structures over channel regions associated with the one or more fins;

forming a single diffusion break cavity in the first region of the substrate;

forming a double diffusion break cavity in the second region of the substrate;

depositing a first dielectric material in the single diffusion break cavity;

depositing a second dielectric material in the double diffusion break cavity;

forming an interlayer dielectric layer between each sacrificial gate structure in the plurality of sacrificial gate structures; and

forming a first hard mask over the interlayer dielectric and the plurality of sacrificial gate structures;

wherein forming the single diffusion break cavity in the first region of the substrate comprises:

forming a patterned hard mask over the first hard mask over the first region;

recessing a non-covered surface of the first hard mask to expose a surface of the interlayer dielectric layer and a first sacrificial gate structure, the first sacrificial gate structure comprising a first gate hard mask, a first gate sidewalls, and a first sacrificial gate material; and

recessing the first gate hard mask of the first sacrificial gate structure and portions of the first gate sidewalls on opposite sides of the first sacrificial gate structure.

2. The method of claim 1 , wherein forming the single diffusion break cavity in the first region of the substrate further comprises forming a spacer on exposed first gate sidewalls of the first hard mask and over the exposed surface of the interlayer dielectric layer.

3. The method of claim 2 , wherein forming the single diffusion break cavity in the first region of the substrate further comprises:

removing portions of the first sacrificial gate material to expose the first gate sidewalls and to expose a surface of the substrate in the first region; and

recessing the exposed surface of the substrate in the first region.

4. The method of claim 3 , wherein depositing the first dielectric material in the single diffusion break cavity comprises depositing the first dielectric material between the first gate sidewalls.

5. The method of claim 1 , wherein forming the double diffusion break cavity in the second region of the substrate comprises:

forming a patterned hard mask over the first hard mask over the second region;

recessing a non-covered surface of the first hard mask to expose:

a surface of the interlayer dielectric layer;

a top portion of a second sacrificial gate structure, the second sacrificial gate structure comprising a second gate hard mask, a second gate sidewall, and a second sacrificial gate material; and

a top portion of a third sacrificial gate structure, the third sacrificial gate structure comprises a third gate hard mask, a third gate sidewall, and a third sacrificial gate material;

recessing an exposed portion of the second gate hard mask and the second gate sidewall to expose a surface of the second sacrificial gate material;

recessing an exposed portion of the third gate hard mask and the third gate sidewall to expose a surface of the third sacrificial gate material; and

forming a dielectric cap over the exposed surfaces of the second sacrificial gate material and the third sacrificial gate material.

6. The method of claim 5 , wherein forming the double diffusion break cavity in the second region of the substrate further comprises:

removing portions of the interlayer dielectric between the second sacrificial gate structure and the third sacrificial gate structure to expose a surface of the substrate in the second region; and

recessing the exposed surface of the substrate in the second region.

7. A method of fabricating a semiconductor device, the method comprising:

forming one or more fins on a substrate, the substrate comprising a first region and a second region;

forming a sacrificial gate insulation layer over channel regions associated with the one or more fins;

forming a plurality of sacrificial gate structures over the channel regions associated with the one or more fins;

forming a single diffusion break cavity in the first region of the substrate;

forming a double diffusion break cavity in the second region of the substrate;

depositing a first dielectric material in the single diffusion break cavity; and

depositing a second dielectric material in the double diffusion break cavity;

forming an interlayer dielectric layer between each sacrificial gate structure in the plurality of sacrificial gate structures; and

forming a first hard mask over the interlayer dielectric and the plurality of sacrificial gate structures;

wherein forming the single diffusion break cavity in the first region of the substrate comprises:

forming a patterned hard mask over the first hard mask over the first region;

recessing a non-covered surface of the first hard mask to expose a surface of the interlayer dielectric layer and a first sacrificial gate structure, the first sacrificial gate structure comprising a first gate hard mask, a first gate sidewalls, and a first sacrificial gate material; and

recessing the first gate hard mask of the first sacrificial gate structure and portions of the first gate sidewalls on opposite sides of the first sacrificial gate structure.

8. The method of claim 7 , wherein forming the single diffusion break cavity in the first region of the substrate further comprises forming a spacer on exposed first gate sidewalls of the first hard mask and over the exposed surface of the interlayer dielectric layer.

9. The method of claim 8 , wherein forming the single diffusion break cavity in the first region of the substrate further comprises:

removing portions of the first sacrificial gate material to expose the first gate sidewalls and to expose a surface of the sacrificial gate insulating layer;

recessing the surface of the sacrificial gate insulation layer to expose a surface of the substrate in the first region; and

recessing the exposed surface of the substrate in the first region.

10. The method of claim 9 , wherein depositing the first dielectric material in the single diffusion break cavity comprises depositing the first dielectric material between the first gate sidewalls.

11. The method of claim 7 , wherein forming the double diffusion break cavity in the second region of the substrate comprises:

forming a patterned hard mask over the first hard mask over the second region;

recessing a non-covered surface of the first hard mask to expose:

a surface of the interlayer dielectric layer,

a top portion of a second sacrificial gate structure, the second sacrificial gate structure comprising a second gate hard mask, a second gate sidewall, and a second sacrificial gate material, and

a top portion of a third sacrificial gate structure, the third sacrificial gate structure comprises a third gate hard mask, a third gate sidewall, and a third sacrificial gate material;

recessing an exposed portion of the second gate hard mask and the second gate sidewall to expose a surface of the second sacrificial gate material;

recessing an exposed portion of the third gate hard mask and the third gate sidewall to expose a surface of the third sacrificial gate material;

forming a dielectric cap over the exposed surfaces of the second sacrificial gate material and the third sacrificial gate material.

12. The method of claim 11 , wherein forming the double diffusion break cavity in the second region of the substrate further comprises:

removing portions of the interlayer dielectric between the second sacrificial gate structure and the third sacrificial gate structure to expose a surface of the substrate in the second region; and

recessing the exposed surface of the substrate in the second region.