Semiconductor device and method

1. A device comprising:

nanostructures comprising a channel region;

a gate dielectric layer on the channel region, the gate dielectric layer having respective portions wrapped around each of the nanostructures;

a first work function tuning layer on the gate dielectric layer, respective portions of the first work function tuning layer completely filling areas between the respective portions of the gate dielectric layer, the first work function tuning layer comprising a n-type work function metal;

a barrier layer on the first work function tuning layer;

a second work function tuning layer on the barrier layer, the second work function tuning layer comprising a p-type work function metal, the p-type work function metal different from the n-type work function metal; and

a fill layer on the second work function tuning layer.

2. The device of claim 1 , wherein the barrier layer comprises amorphous silicon.

3. The device of claim 1 , wherein the barrier layer comprises tantalum nitride.

4. The device of claim 1 , wherein the barrier layer comprises fluorine-free tungsten.

5. The device of claim 1 , wherein the barrier layer has a thickness in a range of 15 Å to 80 Å.

6. A device comprising:

a first transistor comprising:

a first channel region;

a first gate dielectric layer on the first channel region;

a n-type work function tuning layer on the first gate dielectric layer;

a barrier layer on the n-type work function tuning layer;

a first p-type work function tuning layer on the barrier layer;

a first glue layer on the first p-type work function tuning layer; and

a first fill layer on the first glue layer; and

a second transistor comprising:

a second channel region;

a second gate dielectric layer on the second channel region;

a second p-type work function tuning layer on the second gate dielectric layer, the first p-type work function tuning layer and the second p-type work function tuning layer comprising a work function metal;

a second glue layer on the second p-type work function tuning layer, the work function metal of the second p-type work function tuning layer extending continuously between the second gate dielectric layer and the second glue layer; and

a second fill layer on the second glue layer.

7. The device of claim 6 , wherein the first p-type work function tuning layer and the second p-type work function tuning layer further comprise a work function tuning element, the n-type work function tuning layer free of the work function tuning element.

8. The device of claim 7 , wherein the work function tuning element is oxygen.

9. The device of claim 7 , wherein the work function tuning element is fluorine.

10. The device of claim 6 , wherein the first transistor further comprises a first source/drain region adjacent the first channel region, the first source/drain region comprising n-type impurities, and wherein the second transistor further comprises a second source/drain region adjacent the second channel region, the second source/drain region comprising p-type impurities.

11. The device of claim 6 , wherein the barrier layer comprises amorphous silicon.

12. The device of claim 6 , wherein the barrier layer comprises tantalum nitride.

13. The device of claim 6 , wherein the barrier layer comprises fluorine-free tungsten.

14. A method comprising:

depositing a gate dielectric layer having a first portion and a second portion, the first portion deposited on a first channel region, the second portion deposited on a second channel region;

forming a first work function tuning layer on the first portion of the gate dielectric layer;

forming a barrier layer on the first work function tuning layer;

depositing a second work function tuning layer on the barrier layer and the second portion of the gate dielectric layer; and

performing a treatment process on the second work function tuning layer to modify a second work function of the second work function tuning layer, the barrier layer inhibiting modification of a first work function of the first work function tuning layer during the treatment process.

15. The method of claim 14 , wherein depositing the barrier layer comprises depositing amorphous silicon by a CVD process, the CVD process performed with silane, the CVD process performed at a temperature in a range of 300° C. to 500° C., the CVD process performed at a pressure in a range of 2 torr to 35 torr, the barrier layer deposited to a thickness in a range of 15 Å to 80 Å.

16. The method of claim 14 , wherein depositing the barrier layer comprises depositing tantalum nitride by an ALD process, the ALD process performed with pentakis(dimethylamido)tantalum and ammonia, the ALD process performed at a temperature in a range of 250° C. to 450° C., the ALD process performed at a pressure in a range of 2 torr to 35 torr, the barrier layer deposited to a thickness in a range of 15 Å to 80 Å.

17. The method of claim 14 , wherein depositing the barrier layer comprises depositing fluorine-free tungsten by an ALD process, the ALD process performed with tungsten(V) chloride and hydrogen, the ALD process performed at a temperature in a range of 350° C. to 500° C., the ALD process performed at a pressure in a range of 5 torr to 40 torr, the barrier layer deposited to a thickness in a range of 15 Å to 80 Å.

18. The method of claim 14 , wherein the treatment process comprises a fluorination treatment process.

19. The method of claim 14 , wherein the treatment process comprises an oxidation treatment process.

20. The method of claim 14 , wherein forming the first work function tuning layer comprises depositing the first work function tuning layer on the first portion and the second portion of the gate dielectric layer, and wherein forming the barrier layer comprises:

depositing the barrier layer on the first work function tuning layer; and

removing portions of the barrier layer and the first work function tuning layer to expose the second portion of the gate dielectric layer.