Granted Patent B2

US 12,464,817 · App. 18/404,606 · Granted Nov 4, 2025

Inventors: Hsin-Yi Lee (Hsinchu, TW); Weng Chang (Hsinchu, TW); Chi On Chui (Hsinchu, TW)

Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.

H10D84/853H01L21/0228H10D30/024H10D30/6211H10D62/118

Abstract

Claims (44)

1 . A device comprising:

nanostructures comprising a channel region;

a gate dielectric layer on the channel region, wherein respective portions of the gate dielectric layer wrap around each of the nanostructures;

a first work function tuning layer on the gate dielectric layer, the first work function tuning layer comprising an n-type work function metal, wherein respective portions of the first work function tuning layer fill areas between the respective portions of the gate dielectric layer;

a barrier layer on the first work function tuning layer;

a second work function tuning layer on the barrier layer, the second work function tuning layer comprising a p-type work function metal and a work function tuning element, the p-type work function metal different from the n-type work function metal, the second work function tuning layer having more of the work function tuning element than the first work function tuning layer; and

a fill layer on the second work function tuning layer.

2 . The device of claim 1 , wherein the first work function tuning layer further comprises the work function tuning element.

3 . The device of claim 1 , wherein the first work function tuning layer is free of the work function tuning element.

4 . The device of claim 1 , wherein the work function tuning element is oxygen or fluorine.

5 . The device of claim 1 , wherein the barrier layer comprises a barrier material, the barrier material being different from the n-type work function metal, the barrier material being different from the p-type work function metal.

6 . The device of claim 5 , wherein the barrier material is amorphous silicon, tantalum nitride, or fluorine-free tungsten.

7 . The device of claim 1 , further comprising:

a fin extending from a substrate, the fin comprising the channel region.

8 . The device of claim 1 , wherein a thickness of the barrier layer is less than a thickness of the first work function tuning layer and is less than a thickness of the second work function tuning layer.

9 . A device comprising:

a first transistor comprising:

first nanostructures;

a first gate dielectric layer having respective first portions wrapped around each of the first nanostructures;

an n-type work function tuning layer on the first gate dielectric layer, respective portions of the n-type work function tuning layer completely filling areas between the respective first portions of the first gate dielectric layer;

a barrier layer on the n-type work function tuning layer; and

a first p-type work function tuning layer on the barrier layer; and

a second transistor comprising:

second nanostructures;

a second gate dielectric layer having respective second portions wrapped around each of the second nanostructures; and

a second p-type work function tuning layer on the second gate dielectric layer, respective portions of the second p-type work function tuning layer completely filling areas between the respective second portions of the second gate dielectric layer.

10 . The device of claim 1 , wherein the first work function tuning layer and the second work function tuning layer are separated by the barrier layer, wherein the barrier layer has a thickness in a range of 15 Å to 80 Å.

11 . The device of claim 9 , wherein the first p-type work function tuning layer comprises a work function tuning element, the second p-type work function tuning layer comprises the work function tuning element, and the n-type work function tuning layer has less of the work function tuning element than the first p-type work function tuning layer and the second p-type work function tuning layer.

12 . The device of claim 11 , wherein the work function tuning element is oxygen or fluorine.

13 . The device of claim 9 , wherein the first transistor further comprises a first source/drain region adjacent the first nanostructures, the first source/drain region comprising n-type impurities, and wherein the second transistor further comprises a second source/drain region adjacent the second nanostructures, the second source/drain region comprising p-type impurities.

14 . A method comprising:

depositing a gate dielectric layer on a first channel region;

depositing a first work function tuning layer on the gate dielectric layer;

forming a barrier layer on the first work function tuning layer;

depositing a second work function tuning layer on the barrier layer; and

performing a treatment process on the second work function tuning layer to modify a second work function of the second work function tuning layer, the barrier layer covering the first work function tuning layer during the treatment process.

15 . The method of claim 14 , wherein the treatment process incorporates a work function tuning element into the second work function tuning layer.

16 . The method of claim 15 , wherein the work function tuning element is oxygen or fluorine.

17 . The method of claim 14 , wherein forming the barrier layer comprises depositing amorphous silicon by a CVD process.

18 . The method of claim 14 , wherein forming the barrier layer comprises depositing tantalum nitride by an ALD process.

19 . The method of claim 14 , wherein forming the barrier layer comprises depositing fluorine-free tungsten by an ALD process.

20 . The method of claim 14 , further comprising:

depositing the gate dielectric layer on a second channel region; and

removing the barrier layer and the first work function tuning layer from above the second channel region, wherein the barrier layer and the first work function tuning layer remain above the first channel region.

Continuity (4)

References Cited (35)